EP0673062B1 - Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben - Google Patents

Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben Download PDF

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Publication number
EP0673062B1
EP0673062B1 EP95400513A EP95400513A EP0673062B1 EP 0673062 B1 EP0673062 B1 EP 0673062B1 EP 95400513 A EP95400513 A EP 95400513A EP 95400513 A EP95400513 A EP 95400513A EP 0673062 B1 EP0673062 B1 EP 0673062B1
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EP
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Prior art keywords
oxide
layer
etching
trenches
predetermined substrate
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Expired - Lifetime
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EP95400513A
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English (en)
French (fr)
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EP0673062A1 (de
Inventor
Maryse Paoli
Pierre Brouquet
Michel Haond
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Orange SA
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France Telecom SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Definitions

  • the invention relates to the lateral isolation of active areas of a semiconductor substrate by shallow trenches.
  • EP-A-0 407 047 EP-A-0 461 498, EP-A-0 396 369, GB-A-2 256 967, EP-A-0 424 608, EP-A-0 673 061 and JP-A-5 304 219.
  • the object of the invention is to propose a method for isolating active areas by lateral trenches according to claim 1, which can be more easily placed works while ensuring a satisfactory flatness of the surface superior of the device finally obtained by the process, in particularly at the level of large insulating trenches.
  • Another object of the invention is to provide insulation for active areas of semiconductor substrate by lateral trenches, ensuring good electrical insulation and good filling trenches, especially in the case of particularly trenches narrow whose depth / width ratio can become greater than 1 with a width of the order of 0.4 ⁇ m or even less.
  • the definition of predetermined substrate regions intended for subsequently forming the active areas involves carrying out a mask while achieving some of the protruding regions is made from a back mask corresponding to the negative of the mask for defining the predetermined substrate regions.
  • the realization of certain other salient regions may be done from an enlarged back mask compared to the negative of the mask for defining the active zones. This is particularly the case in the presence of active areas adjacent to each other and separated by narrow trenches.
  • step a) prior to the construction of the trenches, a deposit of auxiliary layer on a primary layer of oxide or oxynitride of protection, and the end of attack detection is preferably carried out on the auxiliary layer then acting as a stop layer for the engraving operation.
  • the residual relief height which must not exceed protruding areas of conformal oxide reduced after chemical mechanical polishing is chosen in particular so as not to disturb the stages subsequent photolithography which take place until completion final of the semiconductor component implanted in the substrate. He has been observed that a residual height of 100 nm (1000 ⁇ ) was a limit acceptable.
  • step b While the invention generally provides the use of conformal oxide, it turned out particularly advantageous, in step b), to deposit, in the trenches and on said predetermined substrate regions, a stack comprising a layer of an insulating oxide called flattening oxide placed between two conformal oxide layers. Partial mechanical-chemical polishing of process according to the invention is then carried out on the upper layer compliant oxide of the semiconductor block formed in step d).
  • conformal oxide and leveling oxide makes it easier to fill small cavities, typically having a depth / width ratio greater than or equal to 1. Furthermore, this use of two oxides and in particular of the leveling oxide allows a tolerance for the alignment of the counter mask on the semiconductor substrate which makes it easier to avoid formation of subsequent crevices on either side of the regions active which would cause leakage currents in the component final semiconductor.
  • the insulating material may also include a stack a layer of leveling oxide disposed between two layers compliant oxide.
  • the mode of implementation of the method according to the invention comprises first of all the formation on a semiconductor substrate 1 which can be made of silicon, gallium arsenide or else silicon on insulator type (Silicon On Insulator), a primary layer of oxide 2 such as silicon dioxide SiO 2 or else silicon oxynitride.
  • a semiconductor substrate 1 which can be made of silicon, gallium arsenide or else silicon on insulator type (Silicon On Insulator), a primary layer of oxide 2 such as silicon dioxide SiO 2 or else silicon oxynitride.
  • oxide 2 such as silicon dioxide SiO 2 or else silicon oxynitride.
  • the formation of this primary layer can be carried out by growth or deposition, and one of its functions is to protect the substrate 1.
  • auxiliary oxide layer 3 composed for example of polycrystalline or amorphous silicon or of silicon nitride (Si 3 N 4 ).
  • this auxiliary layer 3 will advantageously serve as a stop layer for a chemical etching operation of the upper layers, with end of attack detection. Its thickness is between 500 and 2000 ⁇ , typically 1000 ⁇ .
  • the layer oxide primer 2 will serve as a stop layer for the etching of this auxiliary layer 3.
  • the thickness of the primary oxide layer must be sufficient to perform the barrier layer function and not too much important not to interfere with the engraving operations. Thickness suitable is between 50 ⁇ and 500 ⁇ .
  • the next step is to define the regions predetermined substrate intended to later form the zones active of the final semiconductor component.
  • a stage of definition conventionally includes a deposit of a resin 4 which is insole through a mask defining active areas then that we develop to finally lead to the structure illustrated on the Figure 1b.
  • the substrate is then chemically etched on both sides of resin 4 then this is removed and it is grown on the block semiconductor an additional layer of oxide, such as dioxide of silicon, so as to obtain a layer 5 making it possible to produce a good interface between the substrate 1 and the future insulating trench 7 as well only to protect the substrate 1 from impurities.
  • the structure obtained at this stage of the process is illustrated in Figure 1c.
  • the region predetermined substrate, intended to subsequently form the zones of the semiconductor component, is referenced 6 and is surmounted by the primary oxide layer 2 and the auxiliary layer 3.
  • the trenches 7 are thus formed on either side of the region 6 and are lined with the additional layer of silicon dioxide 5.
  • a lateral dimension is then defined for these trenches 7, or width, L and a depth P.
  • the next step of the process according to the invention consists in deposit in trenches 7 ( Figure 1d) and on the predetermined region of substrate (or future active area), an insulating material. He was deemed preferable, in particular to more satisfactorily complete the narrow width trenches, lay an insulating stack comprising a layer of a first insulating oxide called "leveling" 9 arranged between two layers 8 and 10 of oxide conforming insulator.
  • planarizing oxide an oxide conformal oxide conforms to the roughness of a substrate on which it is deposited, while a planarizing oxide ("planarizing oxide ”) much more fluid, allows in particular to plug more easily small cavities. This difference between the two oxides can also be analyzed in terms of their surface mobility and is illustrated more particularly in FIGS. 3a and 3b.
  • a predetermined region 6 of substrate has been shown surrounded by trenches, and covered with a layer 8 of conformal oxide.
  • the surface mobility, almost zero for the conformal oxide, is such that the thickness e p of the oxide layer at the foot of the step formed by the side of the active area 6, is substantially equal to or even less than the thickness and of this same layer 8 at the head of the step, which can lead to cavities ("voids") within this conformal oxide when it is used to fill trenches of small width.
  • leveling oxide and oxide conform within a stack can be done by cleavage of the stacked structure, at an isolated active area or even relatively distant from another area, then by chemical revelation with a chemical solution well known to those skilled in the art, for example example based on hydrofluoric acid, allowing a selective attack of the different layers of the stack and finally by an observation using a scanning electron microscope to measure respective thicknesses of the different layers at the foot and at the head of the market.
  • this first conformal oxide layer 8 of which the thickness is advantageously between 1/4 and 1/3, of preferably 1/3, of the minimum width of the trenches on the whole semiconductor wafer, practically achieves the desired electrical insulation function.
  • the second conformal oxide layer allows for almost level the top surface of the stack deposited in wide trenches and which presented after deposit of the flattening oxide of the declivities due to the creep of this oxide over these large areas.
  • planarizing oxides are the same nature and may for example be silicon dioxide. While the planarizing oxide is preferably deposited for example from of the Planar 200 machine from ELECTROTEC, the compliant oxide can be deposited by a conventional CVD deposit (Chemical Vapor Deposition).
  • the thickness of the leveling oxide layer is chosen so that the minimum width trenches existing on the are perfectly filled, i.e. with a variation relief less than 200 ⁇ .
  • An oxide layer thickness flattening between 1000 ⁇ and 2000 ⁇ has been judged satisfactory for a trench width of the order of 0.4 ⁇ m.
  • the thickness of the second oxide layer conforms to 10 has a thickness greater than the sum of the thickness of the stop layer 3 and trench depth. This thickness of the layer 1, was chosen to be 10% higher than said sum which covers dispersions from subsequent etching processes.
  • the next step in the process is to perform on the block semiconductor thus formed, a densification annealing at a temperature at least equal to 900 ° C.
  • a densification annealing at a temperature at least equal to 900 ° C.
  • Such densification annealing well known to those skilled in the art, in particular makes it possible to homogenize the oxide layers deposited which is particularly advantageous for subsequent engraving operations.
  • densification annealing is sufficient to achieve results satisfactory electrical insulation for the semiconductor component (s) final (s), it turned out to be better to anneal densification at a temperature of the order of 1050 ° which leads to optimization of the electrical insulation results of the final component (s).
  • FIGS 1e to 1i illustrate the overall planarization step of the semiconductor block illustrated in Figure 1d.
  • This planing step includes a selective etching partial of the semiconductor block illustrated in FIG. 1d, so that leave on each side of each determined region of substrate of the protruding zones 13 of conformal oxide, then a polishing partial mechanical-chemical properties of the upper oxide layer conforming to the semiconductor block thus etched so as to reduce the height of the protruding areas 13 of conformal oxide below a height of chosen residual relief, then a discovery of the region predetermined corresponding substrate 6 from an etching chemical with end of attack detection performed on the semiconductor block having been mechanically-chemically polished.
  • This planarization step is described in the preferred case of a conformal oxide-leveling oxide-oxide insulating stack compliant. However, it obviously applies to the general case of a single conformal oxide layer of selected thickness, and the advantages of partial chemical mechanical polishing described below also apply to the general case.
  • the definition of the protruding regions 13 is carried out on the basis of a counter mask corresponding to the negative of the definition mask of the active area 6.
  • the use of this mask is part of a step conventional photolithography using a resin 11 deposited on the upper surface of the second conformal oxide layer 10. After sunshine through the back mask and development of the resin, it has a cavity in the extension of the active area 6 12 ( Figure 1e).
  • leveling oxide and conformal oxide makes it possible to obtain on the upper surface of the second conformal oxide layer, located above active area 6, a flat and sufficient surface portion to allow correct alignment of the back mask with the edges of the active area of the substrate, taking into account the alignment tolerances. This avoids the subsequent formation of small cavities on both sides and other of the active area 6 of the substrate and which could have been the consequence of chemical etchings carried out later in back masking performed on a too narrow surface portion.
  • An etching of the oxide layer 10 is then carried out. conform in fixed time so as to remove an equal oxide thickness as the sum of the thickness of the auxiliary layer 3 and the depth P of the trench.
  • the resin 11 is then removed and the structure illustrated in Figure 1f.
  • the upper cavity 20 of the block thus formed is delimited laterally by the steep walls of the protruding points 13.
  • the bottom wall of the cavity 20 is located substantially at the same level as the upper surface of the block located at the outside of the points 13. Furthermore, these points 13 are relatively narrow at the foot with a width at the foot between 0.5 ⁇ m and 1 ⁇ m, typically 0.5 ⁇ m.
  • This partial mechanochemical polishing i.e. carried out for a period leaving residual bumps, offers the advantage of carrying out an essentially mechanical polishing of protruding regions while avoiding an essentially chemical attack large insulating zones located on either side of the regions prominent. This avoids chemically digging these large areas insulators which could lead to depressions in the flat upper surface of the semiconductor device obtained finally by the method according to the invention and illustrated in FIG. 1i.
  • the method according to the invention allows moderate use mechanical chemical polishing which is a particularly step delicate to implement. In practice, it has proved possible obtain softened bumps up to a residual relief height of 200 ⁇ .
  • the next step is to perform a chemical etching, preferably plasma etching, with end of attack detection.
  • This end of attack detection is performed on the stop layer 3.
  • this barrier layer 3 must resist plasma etching and must therefore be composed of a material such as the ratio of the speed of etching of the additional layer 5 of silicon dioxide on the etching speed of the material making up this barrier layer, ie at less than ten.
  • the stop layer 3 is then removed by etching, as that an RIE etching (reactive ion etching) then we proceed to a deoxidation of the predetermined region of substrate 6 so as to obtain the final device illustrated in FIG. 1i.
  • This device D therefore comprises the predetermined substrate region 6 discovered at level of its upper surface and which will later form, after implantation for example, the future active area of a semiconductor component.
  • This future active area 6 is isolated from the other areas active of the substrate by trenches 7 comprising in the present case an oxide stack conforming to 8-leveling oxide 9-oxide conforms to 10.
  • the insulating material of the trench also forms on either side of the predetermined discovery region of the substrate 6, a bump 16 on the flat upper surface of the device D. The height of this bump is less than 1000 ⁇ which will not interfere with any subsequent photolithography steps.

Claims (5)

  1. Verfahren zur Isolierung aktiver Zonen eines Halbleitersubstrats durch seitliche Gräben, dadurch gekennzeichnet, dass:
    a) innerhalb des Halbleitersubstrats (1) Gräben (7) vorgesehen werden, die im Verhältnis zu vorherbestimmten Substratbereichen (6), die dazu gedacht sind, später die aktiven Zonen (6) zu bilden und deren Definition das Ausrühren einer Maske umfasst, seitlich angeordnet sind,
    b) in den Gräben (7) und auf den vorherbestimmten Substratbereichen (6) ein Stapel abgeschieden wird, der eine Schicht aus sogenanntem planarisierenden, isolierenden Oxid (9) umfasst, die zwischen zwei Schichten (8, 10) aus oberflächentreuem, isolierendem Oxid angeordnet ist,
    c) eine Verdichtungsglühung des in Schritt b) gebildeten Halbleiterblocks erfolgt, und
    d) eine teilweise, selektive Gravierung des geglühten Halbleiterblocks erfolgt, um auf beiden Seiten jeden vorherbestimmten Substratbereichs (6) oder auf beiden Seiten von Gruppen benachbarter, vorherbestimmter Substratbereiche (106) hervorspringende Zonen aus oberflächentreuem Oxid (13, 113) übrig zu lassen, die vor der Gravierung definiert wurden, und zwar für einige von ihnen ausgehend von einer Gegerunaske, die dem Negativ der Definitionsmaske der vorherbestimmten Substratbereiche (6) entsprechen, oder von einer im Verhältnis zum Negativ der Definitionsmaske der vorherbestimmten Substratbereiche (106) vergrößerten Gegenmaske,
    e) ein teilweises, chemisch-mechanisches Polieren der oberen Schicht aus oberflächentreuem Oxid (10, 110) des in Schritt d) gebildeten Halbleiterblocks erfolgt, um die Höhe der hervorspringenden Zonen aus oberflächentreuem Oxid unter eine Restreliefhöhe von weniger als 100 nm (1000 Å) zu reduzieren und auf beiden Seiten der vorherbestimmten Substratbereiche Erhebungen übrig zu lassen, deren Höhe kleiner ist als die Restreliefhöhe,
    f) die vorherbestimmten Substratbereiche (6, 106) ausgehend von einer chemischen Gravierung mit Erkennen des Endes des Ätzvorgangs, die auf dem in Schritt e) gebildeten Halbleiterblock erfolgt, aufgedeckt werden.
  2. Verfahren gemäß Anspruch 1, dadurch gekennzeichnet, dass in Schritt a) vor der Ausführung der Gräben (7) eine Abscheidung einer Hilfsschicht (3) auf einer isolierenden Primärschicht erfolgt, und dass das Erkennen des Endes des Ätzvorgangs auf der Hilfsschicht erfolgt, die für den Graviervorgang als Sperrschicht dient.
  3. Verfahren gemäß einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass die chemische Gravierung mit Erkennen des Endes des Ätzvorgangs ein Plasmaätzen ist.
  4. Verfahren gemäß einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der Schritt a) das Ausführen auf dem Halbleitersubstrat einer Primäroxidschicht (2) vor dem Abscheiden der Hilfsschicht (3) umfasst, und dass in Schritt d) die Hilfsschicht (3) und die Primärschicht (2) nach der chemischen Gravierung entfernt werden.
  5. Verfahren gemäß einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Verdichtungsglühung bei einer Temperatur in der Größenordnung von 1050 °C erfolgt.
EP95400513A 1994-03-11 1995-03-10 Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben Expired - Lifetime EP0673062B1 (de)

Applications Claiming Priority (2)

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FR9402871 1994-03-11
FR9402871A FR2717307B1 (fr) 1994-03-11 1994-03-11 Procede d'isolement de zones actives d'un substrat semi-conducteur par tranchees peu profondes quasi planes, et dispositif correspondant

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EP0673062A1 EP0673062A1 (de) 1995-09-20
EP0673062B1 true EP0673062B1 (de) 2002-09-11

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EP (1) EP0673062B1 (de)
JP (1) JPH0837232A (de)
DE (1) DE69528099T2 (de)
FR (1) FR2717307B1 (de)

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US8012847B2 (en) * 2005-04-01 2011-09-06 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
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DE69528099T2 (de) 2003-06-05
JPH0837232A (ja) 1996-02-06
DE69528099D1 (de) 2002-10-17
US5604149A (en) 1997-02-18
FR2717307B1 (fr) 1996-07-19
EP0673062A1 (de) 1995-09-20
FR2717307A1 (fr) 1995-09-15

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