DE69526485D1 - Verfahren zur Herstellung vergrabener Oxidschichten - Google Patents

Verfahren zur Herstellung vergrabener Oxidschichten

Info

Publication number
DE69526485D1
DE69526485D1 DE69526485T DE69526485T DE69526485D1 DE 69526485 D1 DE69526485 D1 DE 69526485D1 DE 69526485 T DE69526485 T DE 69526485T DE 69526485 T DE69526485 T DE 69526485T DE 69526485 D1 DE69526485 D1 DE 69526485D1
Authority
DE
Germany
Prior art keywords
wafer
buried oxide
production
oxide layers
oxygen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69526485T
Other languages
English (en)
Other versions
DE69526485T2 (de
Inventor
John K Lowell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69526485D1 publication Critical patent/DE69526485D1/de
Application granted granted Critical
Publication of DE69526485T2 publication Critical patent/DE69526485T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
DE69526485T 1994-12-12 1995-11-29 Verfahren zur Herstellung vergrabener Oxidschichten Expired - Fee Related DE69526485T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35529894A 1994-12-12 1994-12-12

Publications (2)

Publication Number Publication Date
DE69526485D1 true DE69526485D1 (de) 2002-05-29
DE69526485T2 DE69526485T2 (de) 2002-12-19

Family

ID=23396959

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69526485T Expired - Fee Related DE69526485T2 (de) 1994-12-12 1995-11-29 Verfahren zur Herstellung vergrabener Oxidschichten

Country Status (6)

Country Link
US (1) US5891743A (de)
EP (1) EP0717437B1 (de)
JP (1) JPH08255885A (de)
KR (1) KR960026128A (de)
AT (1) ATE216802T1 (de)
DE (1) DE69526485T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
FR2773261B1 (fr) * 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US6486043B1 (en) 2000-08-31 2002-11-26 International Business Machines Corporation Method of forming dislocation filter in merged SOI and non-SOI chips
FR2823596B1 (fr) 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US6602757B2 (en) * 2001-05-21 2003-08-05 International Business Machines Corporation Self-adjusting thickness uniformity in SOI by high-temperature oxidation of SIMOX and bonded SOI
FR2830983B1 (fr) 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
US7176108B2 (en) 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2899378B1 (fr) 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
CN116759325B (zh) * 2023-08-23 2023-11-03 江苏卓胜微电子股份有限公司 用于监控离子注入剂量的阻值监控方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3622382A (en) * 1969-05-05 1971-11-23 Ibm Semiconductor isolation structure and method of producing
US4151007A (en) * 1977-10-11 1979-04-24 Bell Telephone Laboratories, Incorporated Hydrogen annealing process for stabilizing metal-oxide-semiconductor structures
US4371420A (en) * 1981-03-09 1983-02-01 The United States Of America As Represented By The Secretary Of The Navy Method for controlling impurities in liquid phase epitaxial growth
JPS6031231A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
US4522657A (en) * 1983-10-20 1985-06-11 Westinghouse Electric Corp. Low temperature process for annealing shallow implanted N+/P junctions
JPS6151930A (ja) * 1984-08-22 1986-03-14 Nec Corp 半導体装置の製造方法
JP3066968B2 (ja) * 1988-07-25 2000-07-17 ソニー株式会社 半導体ウエハのゲッタリング方法
US5229311A (en) * 1989-03-22 1993-07-20 Intel Corporation Method of reducing hot-electron degradation in semiconductor devices
JPH03201535A (ja) * 1989-12-28 1991-09-03 Nippon Telegr & Teleph Corp <Ntt> 半導体装置とその製造方法
JPH0411736A (ja) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices

Also Published As

Publication number Publication date
EP0717437B1 (de) 2002-04-24
KR960026128A (de) 1996-07-22
US5891743A (en) 1999-04-06
EP0717437A3 (de) 1997-04-02
DE69526485T2 (de) 2002-12-19
JPH08255885A (ja) 1996-10-01
ATE216802T1 (de) 2002-05-15
EP0717437A2 (de) 1996-06-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee