DE69524050D1 - Gegenimplantationsverfahren bei der herstellung einer halbleitervorrichtung mit selbstausrichtenden ''anti-punchthrough''-gebieten - Google Patents

Gegenimplantationsverfahren bei der herstellung einer halbleitervorrichtung mit selbstausrichtenden ''anti-punchthrough''-gebieten

Info

Publication number
DE69524050D1
DE69524050D1 DE69524050T DE69524050T DE69524050D1 DE 69524050 D1 DE69524050 D1 DE 69524050D1 DE 69524050 T DE69524050 T DE 69524050T DE 69524050 T DE69524050 T DE 69524050T DE 69524050 D1 DE69524050 D1 DE 69524050D1
Authority
DE
Germany
Prior art keywords
counterimplantation
punchthrough
aligning
areas
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69524050T
Other languages
English (en)
Other versions
DE69524050T2 (de
Inventor
Dah-Bin Kao
S Scott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Application granted granted Critical
Publication of DE69524050D1 publication Critical patent/DE69524050D1/de
Publication of DE69524050T2 publication Critical patent/DE69524050T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/919—Compensation doping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69524050T 1994-08-01 1995-07-28 Gegenimplantationsverfahren bei der herstellung einer halbleitervorrichtung mit selbstausrichtenden ''anti-punchthrough''-gebieten Expired - Lifetime DE69524050T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/283,458 US5492847A (en) 1994-08-01 1994-08-01 Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets
PCT/US1995/009510 WO1996004679A1 (en) 1994-08-01 1995-07-28 Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets

Publications (2)

Publication Number Publication Date
DE69524050D1 true DE69524050D1 (de) 2002-01-03
DE69524050T2 DE69524050T2 (de) 2002-07-11

Family

ID=23086164

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69524050T Expired - Lifetime DE69524050T2 (de) 1994-08-01 1995-07-28 Gegenimplantationsverfahren bei der herstellung einer halbleitervorrichtung mit selbstausrichtenden ''anti-punchthrough''-gebieten

Country Status (5)

Country Link
US (1) US5492847A (de)
EP (1) EP0721658B1 (de)
KR (1) KR100373580B1 (de)
DE (1) DE69524050T2 (de)
WO (1) WO1996004679A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3055424B2 (ja) * 1994-04-28 2000-06-26 株式会社デンソー Ｍｉｓ型半導体装置の製造方法
US6417550B1 (en) * 1996-08-30 2002-07-09 Altera Corporation High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage
US6236085B1 (en) 1996-11-11 2001-05-22 Denso Corporation Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate
US5872030A (en) * 1997-10-27 1999-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of improving beta ratio in SRAM and device manufactured thereby
US6051458A (en) * 1998-05-04 2000-04-18 Taiwan Semiconductor Manufacturing Company Drain and source engineering for ESD-protection transistors
US6171913B1 (en) * 1998-09-08 2001-01-09 Taiwan Semiconductor Manufacturing Company Process for manufacturing a single asymmetric pocket implant
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6211023B1 (en) * 1998-11-12 2001-04-03 United Microelectronics Corp. Method for fabricating a metal-oxide semiconductor transistor
US6294432B1 (en) * 1999-12-20 2001-09-25 United Microelectronics Corp. Super halo implant combined with offset spacer process
US6268256B1 (en) * 2000-01-18 2001-07-31 United Microelectronics Corp. Method for reducing short channel effect
JP2002009283A (ja) * 2000-04-19 2002-01-11 Seiko Instruments Inc 半導体素子及びその製造方法
US6274441B1 (en) 2000-04-27 2001-08-14 International Business Machines Corporation Method of forming bitline diffusion halo under gate conductor ledge
US6451675B1 (en) * 2000-09-12 2002-09-17 United Microelectronics Corp. Semiconductor device having varied dopant density regions
US6518135B1 (en) * 2001-09-24 2003-02-11 Integrated Device Technology, Inc. Method for forming localized halo implant regions
KR100464535B1 (ko) * 2002-05-20 2005-01-03 주식회사 하이닉스반도체 반도체소자의 트랜지스터 형성 방법
FR2840453B1 (fr) * 2002-06-04 2005-06-24 St Microelectronics Sa Procede de fabrication d'un transistor mos de longueur de grille reduite, et circuit integre comportant un tel transistor
US7138318B2 (en) * 2003-05-28 2006-11-21 Advanced Micro Devices, Inc. Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate
US7230302B2 (en) * 2004-01-29 2007-06-12 Enpirion, Inc. Laterally diffused metal oxide semiconductor device and method of forming the same
KR100890613B1 (ko) * 2007-01-26 2009-03-27 삼성전자주식회사 마스크롬 소자 및 그 제조 방법
CN103545208B (zh) * 2012-07-11 2018-02-13 中国科学院微电子研究所 半导体器件制造方法
US8673712B2 (en) * 2012-07-20 2014-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Power transistor with high voltage counter implant
US9035380B2 (en) 2012-11-27 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage drain-extended MOSFET having extra drain-OD addition
CN109830538B (zh) 2019-01-22 2022-08-16 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758537A (en) * 1985-09-23 1988-07-19 National Semiconductor Corporation Lateral subsurface zener diode making process
US4745086A (en) * 1985-09-26 1988-05-17 Motorola, Inc. Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation
JPS6437055A (en) * 1987-08-03 1989-02-07 Fujitsu Ltd Mis transistor
US4771014A (en) * 1987-09-18 1988-09-13 Sgs-Thomson Microelectronics, Inc. Process for manufacturing LDD CMOS devices
IT1223571B (it) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte
JP2668538B2 (ja) * 1988-02-05 1997-10-27 ヤマハ株式会社 集積回路装置の製法
JPH021173A (ja) * 1988-06-09 1990-01-05 Fujitsu Ltd Ｍｉｓ電界効果トランジスタ
US5270226A (en) * 1989-04-03 1993-12-14 Matsushita Electric Industrial Co., Ltd. Manufacturing method for LDDFETS using oblique ion implantion technique
US4956311A (en) * 1989-06-27 1990-09-11 National Semiconductor Corporation Double-diffused drain CMOS process using a counterdoping technique

Also Published As

Publication number Publication date
EP0721658B1 (de) 2001-11-21
US5492847A (en) 1996-02-20
WO1996004679A1 (en) 1996-02-15
EP0721658A1 (de) 1996-07-17
KR100373580B1 (ko) 2003-05-16
DE69524050T2 (de) 2002-07-11

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