JPS6437055A - Mis transistor - Google Patents

Mis transistor

Info

Publication number
JPS6437055A
JPS6437055A JP19259287A JP19259287A JPS6437055A JP S6437055 A JPS6437055 A JP S6437055A JP 19259287 A JP19259287 A JP 19259287A JP 19259287 A JP19259287 A JP 19259287A JP S6437055 A JPS6437055 A JP S6437055A
Authority
JP
Japan
Prior art keywords
impurity
tip ends
region
channel region
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19259287A
Other languages
Japanese (ja)
Inventor
Takaaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19259287A priority Critical patent/JPS6437055A/en
Publication of JPS6437055A publication Critical patent/JPS6437055A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the effect of the short channel and restrain the generation of hot carriers so as to restrain a threshold voltage from varying or a carrier movability from decreasing by a method wherein an impurity region used for the prevention of a punch through phenomenon is formed under a impurity region for an LLD structure as tip ends of the channel region of the former recede from tip ends of the channel region of the latter. CONSTITUTION:A MIS transistor is formed, where p-type impurity high concentrated regions 6a and 6b used for the prevention of a punch through phenomenon are formed under n-type impurity low concentrated regions 7a and 7b provided for the formation of a drain region low in impurity concentration as tip ends of the channel region of the former recede from the tip ends of the channel region of the latter. By these processes, a drain is improved in breakdown strength, not only the dielectric breakdown of a drain end is hard to happen, but also the depletion layer which is formed near first impurity regions 5a and 5b when the transistor is in operation is restrained from diffusing, so that a substrate and an insulating layer are protected against deterioration due to the current based on the hot carriers.
JP19259287A 1987-08-03 1987-08-03 Mis transistor Pending JPS6437055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19259287A JPS6437055A (en) 1987-08-03 1987-08-03 Mis transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19259287A JPS6437055A (en) 1987-08-03 1987-08-03 Mis transistor

Publications (1)

Publication Number Publication Date
JPS6437055A true JPS6437055A (en) 1989-02-07

Family

ID=16293839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19259287A Pending JPS6437055A (en) 1987-08-03 1987-08-03 Mis transistor

Country Status (1)

Country Link
JP (1) JPS6437055A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216272A (en) * 1990-04-13 1993-06-01 Nippondenso Co., Ltd. High withstanding voltage MIS transistor
US5371024A (en) * 1988-09-30 1994-12-06 Kabushiki Kaisha Toshiba Semiconductor device and process for manufacturing the same
US5426326A (en) * 1992-08-07 1995-06-20 Hitachi, Ltd. Semiconductor device including arrangement for reducing junction degradation
US5492847A (en) * 1994-08-01 1996-02-20 National Semiconductor Corporation Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets
EP0717448A1 (en) * 1994-12-16 1996-06-19 Sun Microsystems, Inc. Asymmetric low power MOS devices
US5710606A (en) * 1994-08-24 1998-01-20 Kabushiki Kaisha Toshiba LCD TFT having two layer region adjacent base region in which the layers have opposite conductivities and have two density gradients
US5780912A (en) * 1994-08-18 1998-07-14 Sun Microsystems, Inc. Asymmetric low power MOS devices
US5923987A (en) * 1997-06-30 1999-07-13 Sun Microsystems, Inc. Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface
US5985727A (en) * 1997-06-30 1999-11-16 Sun Microsystems, Inc. Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface
US6110783A (en) * 1997-06-27 2000-08-29 Sun Microsystems, Inc. Method for forming a notched gate oxide asymmetric MOS device
US6165827A (en) * 1996-07-09 2000-12-26 Micron Technology, Inc. Semiconductor transistor devices and methods for forming semiconductor transistor devices
US6236085B1 (en) 1996-11-11 2001-05-22 Denso Corporation Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate
US6278162B1 (en) * 1993-06-30 2001-08-21 Integrated Device Technology, Inc. ESD protection for LDD devices

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371024A (en) * 1988-09-30 1994-12-06 Kabushiki Kaisha Toshiba Semiconductor device and process for manufacturing the same
US5342802A (en) * 1990-04-13 1994-08-30 Nippondenso Co., Ltd. Method of manufacturing a complementary MIS transistor
US5216272A (en) * 1990-04-13 1993-06-01 Nippondenso Co., Ltd. High withstanding voltage MIS transistor
US5426326A (en) * 1992-08-07 1995-06-20 Hitachi, Ltd. Semiconductor device including arrangement for reducing junction degradation
US6278162B1 (en) * 1993-06-30 2001-08-21 Integrated Device Technology, Inc. ESD protection for LDD devices
US5492847A (en) * 1994-08-01 1996-02-20 National Semiconductor Corporation Counter-implantation method of manufacturing a semiconductor device with self-aligned anti-punchthrough pockets
US5780912A (en) * 1994-08-18 1998-07-14 Sun Microsystems, Inc. Asymmetric low power MOS devices
US5710606A (en) * 1994-08-24 1998-01-20 Kabushiki Kaisha Toshiba LCD TFT having two layer region adjacent base region in which the layers have opposite conductivities and have two density gradients
EP0717448A1 (en) * 1994-12-16 1996-06-19 Sun Microsystems, Inc. Asymmetric low power MOS devices
US6333539B1 (en) 1996-02-22 2001-12-25 Micron Technology, Inc. Semiconductor transistor devices and methods for forming semiconductor transistor devices
US6165827A (en) * 1996-07-09 2000-12-26 Micron Technology, Inc. Semiconductor transistor devices and methods for forming semiconductor transistor devices
US6236085B1 (en) 1996-11-11 2001-05-22 Denso Corporation Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate
US6110783A (en) * 1997-06-27 2000-08-29 Sun Microsystems, Inc. Method for forming a notched gate oxide asymmetric MOS device
US5923987A (en) * 1997-06-30 1999-07-13 Sun Microsystems, Inc. Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface
US5985727A (en) * 1997-06-30 1999-11-16 Sun Microsystems, Inc. Method for forming MOS devices with retrograde pocket regions and counter dopant regions buried in the substrate surface

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