DE69517888T2 - Auffrischungsverfahren und -schaltungen für Doppelbankspeicher - Google Patents

Auffrischungsverfahren und -schaltungen für Doppelbankspeicher

Info

Publication number
DE69517888T2
DE69517888T2 DE69517888T DE69517888T DE69517888T2 DE 69517888 T2 DE69517888 T2 DE 69517888T2 DE 69517888 T DE69517888 T DE 69517888T DE 69517888 T DE69517888 T DE 69517888T DE 69517888 T2 DE69517888 T2 DE 69517888T2
Authority
DE
Germany
Prior art keywords
circuits
dual bank
bank storage
refreshing
procedures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69517888T
Other languages
English (en)
Other versions
DE69517888D1 (de
Inventor
Michael E Runas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Application granted granted Critical
Publication of DE69517888D1 publication Critical patent/DE69517888D1/de
Publication of DE69517888T2 publication Critical patent/DE69517888T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
DE69517888T 1994-08-16 1995-08-10 Auffrischungsverfahren und -schaltungen für Doppelbankspeicher Expired - Fee Related DE69517888T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/291,155 US5442588A (en) 1994-08-16 1994-08-16 Circuits and methods for refreshing a dual bank memory

Publications (2)

Publication Number Publication Date
DE69517888D1 DE69517888D1 (de) 2000-08-17
DE69517888T2 true DE69517888T2 (de) 2001-01-18

Family

ID=23119101

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69517888T Expired - Fee Related DE69517888T2 (de) 1994-08-16 1995-08-10 Auffrischungsverfahren und -schaltungen für Doppelbankspeicher

Country Status (5)

Country Link
US (1) US5442588A (de)
EP (1) EP0698887B1 (de)
JP (1) JP3186534B2 (de)
KR (1) KR0176739B1 (de)
DE (1) DE69517888T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6301299B1 (en) * 1994-10-28 2001-10-09 Matsushita Electric Industrial Co., Ltd. Memory controller for an ATSC video decoder
WO1996015538A1 (en) * 1994-11-15 1996-05-23 Cirrus Logic, Inc. Circuits, systems, and methods for accounting for defective cells in a memory device
JPH10510634A (ja) * 1994-12-06 1998-10-13 シラス ロジック，インコーポレイテッド 表示画面上へのデータのブロックの表示を制御する回路、システム及び方法
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
US6108015A (en) * 1995-11-02 2000-08-22 Cirrus Logic, Inc. Circuits, systems and methods for interfacing processing circuitry with a memory
US5617555A (en) * 1995-11-30 1997-04-01 Alliance Semiconductor Corporation Burst random access memory employing sequenced banks of local tri-state drivers
JPH09204774A (ja) * 1995-12-22 1997-08-05 Hitachi Ltd 半導体メモリ
US5748968A (en) * 1996-01-05 1998-05-05 Cirrus Logic, Inc. Requesting device capable of canceling its memory access requests upon detecting other specific requesting devices simultaneously asserting access requests
US6504548B2 (en) * 1998-09-18 2003-01-07 Hitachi, Ltd. Data processing apparatus having DRAM incorporated therein
US5881016A (en) * 1997-06-13 1999-03-09 Cirrus Logic, Inc. Method and apparatus for optimizing power consumption and memory bandwidth in a video controller using SGRAM and SDRAM power reduction modes
US5856940A (en) * 1997-08-15 1999-01-05 Silicon Aquarius, Inc. Low latency DRAM cell and method therefor
AU1075599A (en) 1997-10-10 1999-05-03 Rambus Incorporated Dram core refresh with reduced spike current
JP3247647B2 (ja) * 1997-12-05 2002-01-21 株式会社東芝 半導体集積回路装置
US6442667B1 (en) * 1998-06-08 2002-08-27 Texas Instruments Incorporated Selectively powering X Y organized memory banks
US6222786B1 (en) 1999-11-02 2001-04-24 Silicon Aquarius, Inc. Dynamic random access memory with write-without-restore and systems and methods using the same
JP3745185B2 (ja) 2000-03-13 2006-02-15 沖電気工業株式会社 ダイナミックランダムアクセスメモリ
US6445636B1 (en) 2000-08-17 2002-09-03 Micron Technology, Inc. Method and system for hiding refreshes in a dynamic random access memory
JP2002351430A (ja) * 2001-05-30 2002-12-06 Mitsubishi Electric Corp 表示装置
US7290117B2 (en) * 2001-12-20 2007-10-30 Hewlett-Packard Development Company, L.P. Memory having increased data-transfer speed and related systems and methods
US6618314B1 (en) 2002-03-04 2003-09-09 Cypress Semiconductor Corp. Method and architecture for reducing the power consumption for memory devices in refresh operations
US6922350B2 (en) * 2002-09-27 2005-07-26 Intel Corporation Reducing the effect of write disturbs in polymer memories
US7129925B2 (en) * 2003-04-24 2006-10-31 Hewlett-Packard Development Company, L.P. Dynamic self-refresh display memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873096A (ja) * 1981-10-27 1983-05-02 Nec Corp 半導体メモリ
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
JPS6167154A (ja) * 1984-09-11 1986-04-07 Fujitsu Ltd 半導体記憶装置
JPS62241198A (ja) * 1986-04-14 1987-10-21 Hitachi Ltd ダイナミツク型ｒａｍ
US5251177A (en) * 1989-01-23 1993-10-05 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device having an improved refresh operation
JPH02260195A (ja) * 1989-03-30 1990-10-22 Mitsubishi Electric Corp リフレッシュコントロール回路
US5280594A (en) * 1990-07-25 1994-01-18 Advanced Micro Devices, Inc. Architecture for high speed contiguous sequential access memories
US5251178A (en) * 1991-03-06 1993-10-05 Childers Jimmie D Low-power integrated circuit memory
JP2794138B2 (ja) * 1991-08-13 1998-09-03 三菱電機株式会社 半導体記憶装置
JPH05266657A (ja) * 1992-03-23 1993-10-15 Nec Corp ダイナミック型半導体メモリ

Also Published As

Publication number Publication date
JP3186534B2 (ja) 2001-07-11
KR0176739B1 (ko) 1999-05-15
KR960008551A (ko) 1996-03-22
US5442588A (en) 1995-08-15
JPH08190787A (ja) 1996-07-23
EP0698887B1 (de) 2000-07-12
DE69517888D1 (de) 2000-08-17
EP0698887A1 (de) 1996-02-28

Similar Documents

Publication Publication Date Title
DE69517888T2 (de) Auffrischungsverfahren und -schaltungen für Doppelbankspeicher
DE69531090D1 (de) Speicherzelle und Wortleitungstreiber für ASIC-hergestellten integrierten DRAM-Speicher
FI972721A (fi) Sulkukerros käytettäväksi jääkaappien koteloissa
DE69507016T2 (de) Flüssigkeitsaufnahme- und verteilungselement für absorptionskern
DE69424014D1 (de) Burstmode-Auffrischung für DRAMs
DE69511791D1 (de) Redundanzschema für Speicherschaltungen
DE69323681D1 (de) Stressprüfung für Speichernetzwerke in integrierten Schaltungen
DE69720502D1 (de) Zweiseitige aufbewahrungseinheit für informationsträger
DE59705907D1 (de) Wertscheinbehälter für wertscheinausgabeeinheit
NO981435D0 (no) Skriver
DE9412484U1 (de) Aufbewahrungsvorrichtung für Ton- oder Datenträger
DE69638164D1 (de) Integrierte schaltung für multitaskingsunterstützung in einfach- oder mehrfachprozessornetzwerken
KR970010825U (ko) 노테크 플레이어용 메모리 카드 교환기
KR960003880U (ko) 보냉용 컵
DE9406171U1 (de) Ablageplatte für Kühlschränke
KR950031281U (ko) 자동차관리 메모리뱅크
ATA53694A (de) Münzprüfer für automaten u. dergl.
DE9403886U1 (de) Verkaufs- und Lagerschiene für Fläschchen
DE29510281U1 (de) Gesteckkörper für Grab- und Tischgestecke
DE29510258U1 (de) Ablage für Bügeleisen
KR980004386U (ko) 차량용 냉 온장고
DE9410625U1 (de) Aufbewahrungsständer für Daten-, Ton- und/oder Bildträger
KR940024628U (ko) 자동차용 메모받침대
KR960021811U (ko) 자동차의 동전보관 구조
KR970001223U (ko) 자동차용 메모지 보관기구

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee