DE69511639D1 - Verfahren zur Herstellung einer Halbleitervorrichtung und Verarbeitungs-Analyse- und Herstellungsverfahren für deren Substrat - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung und Verarbeitungs-Analyse- und Herstellungsverfahren für deren Substrat

Info

Publication number
DE69511639D1
DE69511639D1 DE69511639T DE69511639T DE69511639D1 DE 69511639 D1 DE69511639 D1 DE 69511639D1 DE 69511639 T DE69511639 T DE 69511639T DE 69511639 T DE69511639 T DE 69511639T DE 69511639 D1 DE69511639 D1 DE 69511639D1
Authority
DE
Germany
Prior art keywords
manufacturing
methods
substrate
semiconductor device
processing analysis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69511639T
Other languages
English (en)
Other versions
DE69511639T2 (de
Inventor
Mokuji Kageyama
Moriya Miyashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69511639D1 publication Critical patent/DE69511639D1/de
Publication of DE69511639T2 publication Critical patent/DE69511639T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Weting (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Sampling And Sample Adjustment (AREA)
DE69511639T 1994-06-30 1995-06-30 Verfahren zur Herstellung einer Halbleitervorrichtung und Verarbeitungs-Analyse- und Herstellungsverfahren für deren Substrat Expired - Lifetime DE69511639T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6171648A JPH0817815A (ja) 1994-06-30 1994-06-30 半導体デバイスの製造方法、半導体基板の処理方法、分析方法及び製造方法

Publications (2)

Publication Number Publication Date
DE69511639D1 true DE69511639D1 (de) 1999-09-30
DE69511639T2 DE69511639T2 (de) 2000-01-13

Family

ID=15927114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69511639T Expired - Lifetime DE69511639T2 (de) 1994-06-30 1995-06-30 Verfahren zur Herstellung einer Halbleitervorrichtung und Verarbeitungs-Analyse- und Herstellungsverfahren für deren Substrat

Country Status (5)

Country Link
US (1) US6037270A (de)
EP (1) EP0690484B1 (de)
JP (1) JPH0817815A (de)
KR (1) KR100215594B1 (de)
DE (1) DE69511639T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11102867A (ja) * 1997-07-16 1999-04-13 Sony Corp 半導体薄膜の形成方法およびプラスチック基板
DE10036867B4 (de) * 1999-07-30 2006-04-13 Tokyo Electron Ltd. Substrat-Bearbeitungsverfahren und -vorrichtung
JP3569662B2 (ja) * 2000-06-26 2004-09-22 三菱住友シリコン株式会社 多結晶シリコンの評価方法
US6849859B2 (en) * 2001-03-21 2005-02-01 Euv Limited Liability Corporation Fabrication of precision optics using an imbedded reference surface
SG121697A1 (en) * 2001-10-25 2006-05-26 Inst Data Storage A method of patterning a substrate
US6689698B2 (en) * 2001-11-13 2004-02-10 Chartered Semiconductor Manufacturing Limited Method for etching a silicided poly using fluorine-based reactive ion etching and sodium hydroxide based solution immersion
JP4006226B2 (ja) * 2001-11-26 2007-11-14 キヤノン株式会社 光学素子の製造方法、光学素子、露光装置及びデバイス製造方法及びデバイス
JP4355799B2 (ja) * 2002-04-22 2009-11-04 株式会社エム光・エネルギー開発研究所 シリコンウエハの研磨方法
JP3795867B2 (ja) * 2003-01-30 2006-07-12 株式会社ルネサステクノロジ エッチング装置、エッチング方法および半導体装置の製造方法
KR100591427B1 (ko) * 2003-02-20 2006-06-21 마츠시타 덴끼 산교 가부시키가이샤 에칭방법, 에칭장치 및 반도체장치의 제조방법
JP4240403B2 (ja) * 2003-12-11 2009-03-18 株式会社Ｓｕｍｃｏ エピタキシャルウェーハの製造方法
KR100561005B1 (ko) * 2003-12-30 2006-03-16 동부아남반도체 주식회사 반도체 소자의 제조 방법
DE102006023497B4 (de) 2006-05-18 2008-05-29 Siltronic Ag Verfahren zur Behandlung einer Halbleiterscheibe
JP4772610B2 (ja) * 2006-07-19 2011-09-14 東京エレクトロン株式会社 分析方法
US8261730B2 (en) * 2008-11-25 2012-09-11 Cambridge Energy Resources Inc In-situ wafer processing system and method
JP5674832B2 (ja) * 2012-01-25 2015-02-25 富士フイルム株式会社 キャパシタ形成方法、半導体基板製品の製造方法、およびエッチング液
JP7126468B2 (ja) * 2019-03-20 2022-08-26 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法および基板処理装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2680482B2 (ja) * 1990-06-25 1997-11-19 株式会社東芝 半導体基板、半導体基板と半導体装置の製造方法、並びに半導体基板の検査・評価方法
JPS6057937A (ja) * 1983-09-09 1985-04-03 Ushio Inc 紫外線洗浄方法
JPS614576A (ja) * 1984-06-15 1986-01-10 Hoya Corp スプレ−方法
DE4002327A1 (de) * 1990-01-26 1991-08-01 Wacker Chemitronic Verfahren zur nasschemischen behandlung von halbleiteroberflaechen und loesung zu seiner durchfuehrung
JPH0415614A (ja) * 1990-05-09 1992-01-21 Ricoh Co Ltd 変位拡大装置
JP2653566B2 (ja) * 1991-03-27 1997-09-17 株式会社東芝 半導体基板評価方法及び装置
US5238529A (en) * 1992-04-20 1993-08-24 Texas Instruments Incorporated Anisotropic metal oxide etch
EP0567939A3 (en) * 1992-04-29 1993-12-15 Texas Instruments Inc Method of removing small particles from a surface
US5234540A (en) * 1992-04-30 1993-08-10 Submicron Systems, Inc. Process for etching oxide films in a sealed photochemical reactor
US5464480A (en) * 1993-07-16 1995-11-07 Legacy Systems, Inc. Process and apparatus for the treatment of semiconductor wafers in a fluid

Also Published As

Publication number Publication date
JPH0817815A (ja) 1996-01-19
EP0690484B1 (de) 1999-08-25
KR960002601A (ko) 1996-01-26
DE69511639T2 (de) 2000-01-13
KR100215594B1 (ko) 1999-08-16
US6037270A (en) 2000-03-14
EP0690484A1 (de) 1996-01-03

Similar Documents

Publication Publication Date Title
DE69317805D1 (de) Substrat für eine Halbleitervorrichtung und Verfahren zur Vorbereitung desselben
DE69511639D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung und Verarbeitungs-Analyse- und Herstellungsverfahren für deren Substrat
DE69403593D1 (de) Gerät und Verfahren zur Herstellung einer Halbleitervorrichtung
DE69526895D1 (de) Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe
DE69425643D1 (de) Reinigungsmittel für Halbleiter-Anordnung und Verfahren zur Herstellung einer Halbleiter-Anordnung
DE69528611D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
DE69602686D1 (de) Verfahren zur Herstellung einer Elektrodenstruktur für eine Halbleitervorrichtung
DE69703052D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung und Verwendung eines Spülmittels zur Halbleiter-Reinigung
DE69425632D1 (de) Verfahren zur Herstellung einer kristallisierten Halbleiterschicht und diese verwendender Halbleitervorrichtungen
DE69514201D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE69209488D1 (de) Verfahren zur Herstellung eines Halbleiterplätchens und Substrat für die Herstellung eines Halbleiters
DE69228787D1 (de) Verfahren und Anlage zur Herstellung von Halbleitervorrichtungen
DE69209678D1 (de) Halbleiteranordnung für Hochspannungsverwendung und Verfahren zur Herstellung
DE69631233D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69120371D1 (de) Verfahren zur Herstellung einer dünnen Schicht und Halbleitervorrichtungen
DE69417463D1 (de) Klebeträger für Wafer und Verfahren zur Herstellung von Halbleiterbauelementen mit diesem Träger
DE69515189D1 (de) SOI-Substrat und Verfahren zur Herstellung
DE69627215D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE69333152D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
DE69331815D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
DE68921501D1 (de) Verfahren zur Herstellung einer Waferhalteeinrichtung für Anlagen zur schnellen thermischen Behandlung.
DE69331816D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69332231D1 (de) Halbleitersubstrat und Verfahren zu seiner Herstellung
DE69127582D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates
DE69503532D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition