DE69504203D1 - Mehrtorige datenspeicheranordnung mit mehrfachen spaltengruppen - Google Patents
Mehrtorige datenspeicheranordnung mit mehrfachen spaltengruppenInfo
- Publication number
- DE69504203D1 DE69504203D1 DE69504203T DE69504203T DE69504203D1 DE 69504203 D1 DE69504203 D1 DE 69504203D1 DE 69504203 T DE69504203 T DE 69504203T DE 69504203 T DE69504203 T DE 69504203T DE 69504203 D1 DE69504203 D1 DE 69504203D1
- Authority
- DE
- Germany
- Prior art keywords
- port
- sam
- random access
- access memory
- data storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Dram (AREA)
- Shift Register Type Memory (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/323,179 US5490112A (en) | 1993-02-05 | 1994-10-14 | Multi-port memory device with multiple sets of columns |
PCT/US1995/012677 WO1996012286A1 (en) | 1994-10-14 | 1995-10-03 | Multi-port memory device with multiple sets of columns |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69504203D1 true DE69504203D1 (de) | 1998-09-24 |
DE69504203T2 DE69504203T2 (de) | 1999-01-07 |
Family
ID=23258057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69504203T Expired - Lifetime DE69504203T2 (de) | 1994-10-14 | 1995-10-03 | Mehrtorige datenspeicheranordnung mit mehrfachen spaltengruppen |
Country Status (7)
Country | Link |
---|---|
US (1) | US5490112A (de) |
EP (1) | EP0786136B1 (de) |
JP (1) | JP3111194B2 (de) |
KR (1) | KR100280989B1 (de) |
AT (1) | ATE170021T1 (de) |
DE (1) | DE69504203T2 (de) |
WO (1) | WO1996012286A1 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5659518A (en) * | 1995-05-22 | 1997-08-19 | Micron Technology, Inc. | Multi-port memory with multiple function access cycles and transfers with simultaneous random access |
US5657266A (en) * | 1995-06-30 | 1997-08-12 | Micron Technology, Inc. | Single ended transfer circuit |
JPH09134590A (ja) * | 1995-09-04 | 1997-05-20 | Mitsubishi Electric Corp | 半導体記憶回路装置及びその設計装置 |
US5799209A (en) * | 1995-12-29 | 1998-08-25 | Chatter; Mukesh | Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration |
US5774408A (en) * | 1997-01-28 | 1998-06-30 | Micron Technology, Inc. | DRAM architecture with combined sense amplifier pitch |
AU744329B2 (en) * | 1997-04-30 | 2002-02-21 | Canon Kabushiki Kaisha | Data normalization circuit and method |
US6118462A (en) | 1997-07-01 | 2000-09-12 | Memtrax Llc | Computer system controller having internal memory and external memory control |
US6085290A (en) * | 1998-03-10 | 2000-07-04 | Nexabit Networks, Llc | Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM) |
US6138219A (en) * | 1998-03-27 | 2000-10-24 | Nexabit Networks Llc | Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access |
US6259634B1 (en) * | 2000-05-22 | 2001-07-10 | Silicon Access Networks, Inc. | Pseudo dual-port DRAM for simultaneous read/write access |
JP2003233986A (ja) * | 2002-02-07 | 2003-08-22 | Sony Corp | 半導体記憶装置 |
KR100532433B1 (ko) * | 2003-05-07 | 2005-11-30 | 삼성전자주식회사 | 하나의 패드를 통하여 데이터를 동시에 입출력하기 위한장치 및 방법 |
US7238218B2 (en) * | 2004-04-06 | 2007-07-03 | International Business Machines Corporation | Memory prefetch method and system |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
KR100634566B1 (ko) | 2005-10-06 | 2006-10-16 | 엠텍비젼 주식회사 | 공유 메모리 제어 방법 및 공유 메모리 동작 제어를수행하는 사용자 단말기 |
KR100843580B1 (ko) | 2006-05-24 | 2008-07-04 | 엠텍비젼 주식회사 | 접근 권한 레지스터 로직을 갖는 다중 포트 메모리 장치 및그 제어 방법 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4851834A (en) * | 1984-01-19 | 1989-07-25 | Digital Equipment Corp. | Multiport memory and source arrangement for pixel information |
JPS634493A (ja) * | 1986-06-24 | 1988-01-09 | Mitsubishi Electric Corp | デユアルポ−トメモリ |
JPH0740430B2 (ja) * | 1986-07-04 | 1995-05-01 | 日本電気株式会社 | メモリ装置 |
US4891794A (en) * | 1988-06-20 | 1990-01-02 | Micron Technology, Inc. | Three port random access memory |
JP3028963B2 (ja) * | 1988-09-21 | 2000-04-04 | 株式会社東芝 | ビデオメモリ装置 |
JP3061824B2 (ja) * | 1989-12-18 | 2000-07-10 | 松下電子工業株式会社 | 半導体メモリ |
KR950003605B1 (ko) * | 1990-04-27 | 1995-04-14 | 가부시키가이샤 도시바 | 반도체 기억장치 |
US5121360A (en) * | 1990-06-19 | 1992-06-09 | International Business Machines Corporation | Video random access memory serial port access |
JP2753129B2 (ja) * | 1990-10-02 | 1998-05-18 | 株式会社東芝 | 半導体記憶装置 |
JP2928654B2 (ja) * | 1991-04-10 | 1999-08-03 | 株式会社東芝 | マルチポートdram |
JP2999845B2 (ja) * | 1991-04-25 | 2000-01-17 | 沖電気工業株式会社 | シリアルアクセスメモリの倍速コントロール方式 |
JPH056690A (ja) * | 1991-06-28 | 1993-01-14 | Mitsubishi Electric Corp | デユアルポートメモリ |
US5381376A (en) * | 1991-11-22 | 1995-01-10 | Samsung Electronics Co., Ltd. | Video RAM having block selection function during serial write transfer operation |
-
1994
- 1994-10-14 US US08/323,179 patent/US5490112A/en not_active Expired - Lifetime
-
1995
- 1995-10-03 WO PCT/US1995/012677 patent/WO1996012286A1/en active IP Right Grant
- 1995-10-03 EP EP95937321A patent/EP0786136B1/de not_active Expired - Lifetime
- 1995-10-03 DE DE69504203T patent/DE69504203T2/de not_active Expired - Lifetime
- 1995-10-03 JP JP08513271A patent/JP3111194B2/ja not_active Expired - Lifetime
- 1995-10-03 KR KR1019970702411A patent/KR100280989B1/ko not_active IP Right Cessation
- 1995-10-03 AT AT95937321T patent/ATE170021T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5490112A (en) | 1996-02-06 |
ATE170021T1 (de) | 1998-09-15 |
WO1996012286A1 (en) | 1996-04-25 |
JPH09511861A (ja) | 1997-11-25 |
JP3111194B2 (ja) | 2000-11-20 |
KR100280989B1 (ko) | 2001-02-01 |
KR970707551A (ko) | 1997-12-01 |
EP0786136A1 (de) | 1997-07-30 |
EP0786136B1 (de) | 1998-08-19 |
DE69504203T2 (de) | 1999-01-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: ANWALTSKANZLEI GULDE HENGELHAUPT ZIEBIG & SCHNEIDE |