WO1997011419A3 - Synchronous multi-port random access memory - Google Patents
Synchronous multi-port random access memory Download PDFInfo
- Publication number
- WO1997011419A3 WO1997011419A3 PCT/US1996/014311 US9614311W WO9711419A3 WO 1997011419 A3 WO1997011419 A3 WO 1997011419A3 US 9614311 W US9614311 W US 9614311W WO 9711419 A3 WO9711419 A3 WO 9711419A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- random access
- access memory
- port random
- synchronous multi
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0853—Cache with multiport tag or data arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/30—Providing cache or TLB in specific location of a processing system
- G06F2212/304—In main memory subsystem
- G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A synchronous multi-port random access memory (200) has a plurality of memory arrays (208). Each memory array having a plurality of memory cells arranged in a predetermined number of rows and a predetermined number of columns. The columns of each memory array are interleaved. Each of a plurality of memory ports (201) has a subcache (204) coupled thereto for each connection between each of the plurality of memory ports. A programmable controller (212) enables the memory cells to enable the cells in interleaved groups responsive to address signals and applies control signals to the memory arrays, to the memory ports, and the caches.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US52585695A | 1995-09-08 | 1995-09-08 | |
US08/525,856 | 1995-09-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1997011419A2 WO1997011419A2 (en) | 1997-03-27 |
WO1997011419A3 true WO1997011419A3 (en) | 1997-04-24 |
Family
ID=24094880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/014311 WO1997011419A2 (en) | 1995-09-08 | 1996-09-06 | Synchronous multi-port random access memory |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO1997011419A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6212597B1 (en) * | 1997-07-28 | 2001-04-03 | Neonet Lllc | Apparatus for and method of architecturally enhancing the performance of a multi-port internally cached (AMPIC) DRAM array and like |
DE19937176A1 (en) * | 1999-08-06 | 2001-02-15 | Siemens Ag | Multiprocessor system |
US8250312B2 (en) * | 2009-04-29 | 2012-08-21 | Micron Technology, Inc. | Configurable multi-port memory devices and methods |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4783731A (en) * | 1982-07-15 | 1988-11-08 | Hitachi, Ltd. | Multicomputer system having dual common memories |
US4930066A (en) * | 1985-10-15 | 1990-05-29 | Agency Of Industrial Science And Technology | Multiport memory system |
US5127014A (en) * | 1990-02-13 | 1992-06-30 | Hewlett-Packard Company | Dram on-chip error correction/detection |
US5283877A (en) * | 1990-07-17 | 1994-02-01 | Sun Microsystems, Inc. | Single in-line DRAM memory module including a memory controller and cross bar switches |
US5386511A (en) * | 1991-04-22 | 1995-01-31 | International Business Machines Corporation | Multiprocessor system and data transmission apparatus thereof |
-
1996
- 1996-09-06 WO PCT/US1996/014311 patent/WO1997011419A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4783731A (en) * | 1982-07-15 | 1988-11-08 | Hitachi, Ltd. | Multicomputer system having dual common memories |
US4930066A (en) * | 1985-10-15 | 1990-05-29 | Agency Of Industrial Science And Technology | Multiport memory system |
US5127014A (en) * | 1990-02-13 | 1992-06-30 | Hewlett-Packard Company | Dram on-chip error correction/detection |
US5283877A (en) * | 1990-07-17 | 1994-02-01 | Sun Microsystems, Inc. | Single in-line DRAM memory module including a memory controller and cross bar switches |
US5386511A (en) * | 1991-04-22 | 1995-01-31 | International Business Machines Corporation | Multiprocessor system and data transmission apparatus thereof |
Also Published As
Publication number | Publication date |
---|---|
WO1997011419A2 (en) | 1997-03-27 |
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