DE69433542D1 - Prüfung, sequenziellogischer Schaltung auf grund einer kombinatorischen Logikschaltungsveränderung - Google Patents

Prüfung, sequenziellogischer Schaltung auf grund einer kombinatorischen Logikschaltungsveränderung

Info

Publication number
DE69433542D1
DE69433542D1 DE69433542T DE69433542T DE69433542D1 DE 69433542 D1 DE69433542 D1 DE 69433542D1 DE 69433542 T DE69433542 T DE 69433542T DE 69433542 T DE69433542 T DE 69433542T DE 69433542 D1 DE69433542 D1 DE 69433542D1
Authority
DE
Germany
Prior art keywords
logic circuit
testing
sequential
combinatorial
change
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69433542T
Other languages
English (en)
Other versions
DE69433542T2 (de
Inventor
Manoj Sachdev
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69433542D1 publication Critical patent/DE69433542D1/de
Publication of DE69433542T2 publication Critical patent/DE69433542T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G01R31/3008—Quiescent current [IDDQ] test or leakage current test
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69433542T 1993-07-09 1994-07-05 Prüfung, sequenziellogischer Schaltung auf grund einer kombinatorischen Logikschaltungsveränderung Expired - Fee Related DE69433542T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP93202027 1993-07-09
EP93202027 1993-07-09

Publications (2)

Publication Number Publication Date
DE69433542D1 true DE69433542D1 (de) 2004-03-18
DE69433542T2 DE69433542T2 (de) 2004-12-23

Family

ID=8213972

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69433542T Expired - Fee Related DE69433542T2 (de) 1993-07-09 1994-07-05 Prüfung, sequenziellogischer Schaltung auf grund einer kombinatorischen Logikschaltungsveränderung

Country Status (8)

Country Link
US (1) US6134688A (de)
EP (1) EP0633530B1 (de)
JP (1) JP3618370B2 (de)
KR (1) KR100350560B1 (de)
DE (1) DE69433542T2 (de)
MY (1) MY112568A (de)
SG (1) SG52788A1 (de)
TW (1) TW222725B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69531597T2 (de) * 1994-07-05 2004-06-24 Koninklijke Philips Electronics N.V. Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreis
EP0786170A1 (de) * 1995-08-14 1997-07-30 Koninklijke Philips Electronics N.V. Mos master-slave flip flop mit reduzierter anzahl von durchgangsgattern
JP2947204B2 (ja) 1997-02-24 1999-09-13 日本電気株式会社 Ｌｓｉの故障箇所の特定化方法
DE19742946C2 (de) * 1997-09-29 2000-10-12 Siemens Ag Testschaltung auf einem Halbleiter-Chip
AU1726000A (en) * 1998-11-13 2000-06-05 Broadcom Corporation Dynamic register with iddq testing capability
JP2002333462A (ja) * 2001-05-08 2002-11-22 Matsushita Electric Ind Co Ltd 集積回路、及び集積回路のテスト方法
KR20030006581A (ko) * 2001-07-13 2003-01-23 주식회사 갓바위 천연물 배지로 배양된 홍국 및 홍국을 이용한 주류의제조방법
KR100524936B1 (ko) * 2002-12-05 2005-10-31 삼성전자주식회사 셀프 테스트를 위한 입력 신호 발생 기능을 갖는 ｓｂｄ 버퍼 및 ｓｂｄ 버퍼의 셀프 테스트 방법
JP5087278B2 (ja) * 2003-11-12 2012-12-05 エヌエックスピー ビー ヴィ 電子回路における電力消費ピークの制御
JP2005156183A (ja) * 2003-11-20 2005-06-16 Toshiba Microelectronics Corp スキャンテスト回路
US7895560B2 (en) * 2006-10-02 2011-02-22 William Stuart Lovell Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects
JP2010003388A (ja) * 2008-06-23 2010-01-07 Elpida Memory Inc 半導体記憶装置およびそのテスト方法
CN104898038A (zh) * 2015-05-26 2015-09-09 大连理工大学 一种利用扫描链获取芯片逻辑结构的方法
KR102197252B1 (ko) 2019-04-03 2020-12-31 박만기 꼬막종패 양식용 그물망
KR102319127B1 (ko) * 2020-07-14 2021-11-01 주식회사 엑시콘 비동기 패턴 데이터를 제공하는 피검사 디바이스 테스트 시스템
KR102473973B1 (ko) 2021-03-17 2022-12-02 박만기 꼬막종패 양식용 그물망

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3009945A1 (de) * 1979-03-15 1980-09-18 Nippon Electric Co Integrierter, logischer schaltkreis mit funktionspruefung
JPS56153838A (en) * 1980-04-28 1981-11-28 Nippon Telegr & Teleph Corp <Ntt> Method for converting sequential circuit into combinatorial circuit
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
JPS5789154A (en) * 1980-11-25 1982-06-03 Nec Corp Logical integrated circuit
US4855669A (en) * 1987-10-07 1989-08-08 Xilinx, Inc. System for scan testing of logic circuit networks
FR2670299B1 (fr) * 1990-12-07 1993-01-22 Thomson Composants Militaires Circuit integre avec controleur de test peripherique.
JP3057814B2 (ja) * 1991-06-26 2000-07-04 日本電気株式会社 半導体集積回路
US5533032A (en) * 1991-10-28 1996-07-02 Sequoia Semiconductor, Inc. Built-in self-test global clock drive architecture
JPH05121666A (ja) * 1991-10-29 1993-05-18 Nec Corp 半導体集積論理回路
JP2817486B2 (ja) * 1991-11-29 1998-10-30 日本電気株式会社 論理集積回路
JP2871291B2 (ja) * 1992-05-20 1999-03-17 日本電気株式会社 論理集積回路

Also Published As

Publication number Publication date
TW222725B (en) 1994-04-21
JPH07146341A (ja) 1995-06-06
SG52788A1 (en) 1998-09-28
MY112568A (en) 2001-07-31
US6134688A (en) 2000-10-17
DE69433542T2 (de) 2004-12-23
EP0633530B1 (de) 2004-02-11
KR100350560B1 (ko) 2002-12-12
EP0633530A3 (de) 1998-06-17
JP3618370B2 (ja) 2005-02-09
KR960016134A (ko) 1996-05-22
EP0633530A2 (de) 1995-01-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee