DE69429690D1 - Verfahren zur Bildung eines leitfähigen Musters auf einem Substrat - Google Patents

Verfahren zur Bildung eines leitfähigen Musters auf einem Substrat

Info

Publication number
DE69429690D1
DE69429690D1 DE69429690T DE69429690T DE69429690D1 DE 69429690 D1 DE69429690 D1 DE 69429690D1 DE 69429690 T DE69429690 T DE 69429690T DE 69429690 T DE69429690 T DE 69429690T DE 69429690 D1 DE69429690 D1 DE 69429690D1
Authority
DE
Germany
Prior art keywords
substrate
forming
conductive pattern
conductive
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69429690T
Other languages
English (en)
Other versions
DE69429690T2 (de
Inventor
Yoshiaki Kohno
Tatsuya Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Application granted granted Critical
Publication of DE69429690D1 publication Critical patent/DE69429690D1/de
Publication of DE69429690T2 publication Critical patent/DE69429690T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09963—Programming circuit by using small elements, e.g. small PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
DE1994629690 1993-06-10 1994-06-07 Verfahren zur Bildung eines leitfähigen Musters auf einem Substrat Expired - Lifetime DE69429690T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13860393A JP3252534B2 (ja) 1993-06-10 1993-06-10 基板への導電パターン形成方法

Publications (2)

Publication Number Publication Date
DE69429690D1 true DE69429690D1 (de) 2002-03-14
DE69429690T2 DE69429690T2 (de) 2002-10-17

Family

ID=15225955

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1994629690 Expired - Lifetime DE69429690T2 (de) 1993-06-10 1994-06-07 Verfahren zur Bildung eines leitfähigen Musters auf einem Substrat

Country Status (3)

Country Link
EP (1) EP0629110B1 (de)
JP (1) JP3252534B2 (de)
DE (1) DE69429690T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3099640B2 (ja) * 1994-06-14 2000-10-16 株式会社村田製作所 焼結体内蔵抵抗体の製造方法及び積層セラミック電子部品の製造方法
US6871396B2 (en) * 2000-02-09 2005-03-29 Matsushita Electric Industrial Co., Ltd. Transfer material for wiring substrate
EP2355144A1 (de) * 2010-02-09 2011-08-10 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO Bestückung auf flexiblen und/oder dehnbaren Substraten

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0754780B2 (ja) * 1987-08-10 1995-06-07 株式会社村田製作所 積層セラミックコンデンサの製造方法
JPH04122093A (ja) * 1990-09-13 1992-04-22 Fujitsu Ltd ペーストの転写方法と転写治具
JP2990621B2 (ja) * 1990-11-05 1999-12-13 株式会社村田製作所 積層セラミック電子部品の製造方法

Also Published As

Publication number Publication date
EP0629110A3 (de) 1996-04-24
EP0629110A2 (de) 1994-12-14
JPH06350225A (ja) 1994-12-22
DE69429690T2 (de) 2002-10-17
EP0629110B1 (de) 2002-01-23
JP3252534B2 (ja) 2002-02-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition