DE69429122T2 - Verfahren zum Schützen der Oberfläche eines halbleitenden Substrats während des Schleifens - Google Patents

Verfahren zum Schützen der Oberfläche eines halbleitenden Substrats während des Schleifens

Info

Publication number
DE69429122T2
DE69429122T2 DE69429122T DE69429122T DE69429122T2 DE 69429122 T2 DE69429122 T2 DE 69429122T2 DE 69429122 T DE69429122 T DE 69429122T DE 69429122 T DE69429122 T DE 69429122T DE 69429122 T2 DE69429122 T2 DE 69429122T2
Authority
DE
Germany
Prior art keywords
protecting
substrate during
during grinding
semiconducting substrate
semiconducting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69429122T
Other languages
English (en)
Other versions
DE69429122D1 (de
Inventor
Franklin L Allen
Lawrence D Dallas Dyer
Vikki S Sherman Simpson
Michael Anna Cunningham
Eugene C Sherman Davis
Jerry B Van Alstyne Medders
Jerry D Sherman Smith
John B Robbins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69429122D1 publication Critical patent/DE69429122D1/de
Application granted granted Critical
Publication of DE69429122T2 publication Critical patent/DE69429122T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE69429122T 1993-01-19 1994-01-19 Verfahren zum Schützen der Oberfläche eines halbleitenden Substrats während des Schleifens Expired - Fee Related DE69429122T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/005,713 US5424224A (en) 1993-01-19 1993-01-19 Method of surface protection of a semiconductor wafer during polishing

Publications (2)

Publication Number Publication Date
DE69429122D1 DE69429122D1 (de) 2002-01-03
DE69429122T2 true DE69429122T2 (de) 2002-06-20

Family

ID=21717325

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69429122T Expired - Fee Related DE69429122T2 (de) 1993-01-19 1994-01-19 Verfahren zum Schützen der Oberfläche eines halbleitenden Substrats während des Schleifens

Country Status (4)

Country Link
US (1) US5424224A (de)
EP (1) EP0607940B1 (de)
JP (1) JPH06349796A (de)
DE (1) DE69429122T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2719113B2 (ja) * 1994-05-24 1998-02-25 信越半導体株式会社 単結晶シリコンウェーハの歪付け方法
US5958794A (en) * 1995-09-22 1999-09-28 Minnesota Mining And Manufacturing Company Method of modifying an exposed surface of a semiconductor wafer
JPH09270400A (ja) * 1996-01-31 1997-10-14 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法
JP3339545B2 (ja) * 1996-05-22 2002-10-28 信越半導体株式会社 半導体ウエーハの製造方法
JP3620679B2 (ja) * 1996-08-27 2005-02-16 信越半導体株式会社 遊離砥粒によるウエーハの面取装置及び面取方法
US5780204A (en) * 1997-02-03 1998-07-14 Advanced Micro Devices, Inc. Backside wafer polishing for improved photolithography
DE19704546A1 (de) * 1997-02-06 1998-08-13 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer einseitig beschichteten und mit einem Finish versehenen Halbleiterscheibe
US6194317B1 (en) 1998-04-30 2001-02-27 3M Innovative Properties Company Method of planarizing the upper surface of a semiconductor wafer
US8092707B2 (en) 1997-04-30 2012-01-10 3M Innovative Properties Company Compositions and methods for modifying a surface suited for semiconductor fabrication
JPH10309666A (ja) * 1997-05-09 1998-11-24 Speedfam Co Ltd エッジポリッシング装置及びその方法
US6080042A (en) * 1997-10-31 2000-06-27 Virginia Semiconductor, Inc. Flatness and throughput of single side polishing of wafers
US6023094A (en) 1998-01-14 2000-02-08 National Semiconductor Corporation Semiconductor wafer having a bottom surface protective coating
DE19915078A1 (de) 1999-04-01 2000-10-12 Siemens Ag Verfahren zur Prozessierung einer monokristallinen Halbleiterscheibe und teilweise prozessierte Halbleiterscheibe
US6245677B1 (en) * 1999-07-28 2001-06-12 Noor Haq Backside chemical etching and polishing
US6376335B1 (en) 2000-02-17 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
US6622334B1 (en) 2000-03-29 2003-09-23 International Business Machines Corporation Wafer edge cleaning utilizing polish pad material
US6709981B2 (en) 2000-08-16 2004-03-23 Memc Electronic Materials, Inc. Method and apparatus for processing a semiconductor wafer using novel final polishing method
US6790125B2 (en) * 2000-12-11 2004-09-14 International Business Machines Corporation Backside integrated circuit die surface finishing technique and tool
US6852241B2 (en) 2001-08-14 2005-02-08 Lexmark International, Inc. Method for making ink jet printheads
US7018268B2 (en) * 2002-04-09 2006-03-28 Strasbaugh Protection of work piece during surface processing
US8339904B2 (en) * 2005-06-28 2012-12-25 Eta Sa Manufacture Horlogère Suisse Reinforced micro-mechanical part
US7559825B2 (en) * 2006-12-21 2009-07-14 Memc Electronic Materials, Inc. Method of polishing a semiconductor wafer
JP5795461B2 (ja) * 2009-08-19 2015-10-14 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
CN102044432B (zh) * 2009-10-13 2012-12-05 中芯国际集成电路制造(上海)有限公司 防止晶圆表面不平及曝光中失焦的方法
CN115256108B (zh) * 2022-07-12 2023-12-19 山东润马光能科技有限公司 一种浮动式晶圆边缘打磨方法及装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4384919A (en) * 1978-11-13 1983-05-24 Sperry Corporation Method of making x-ray masks
JPS5958827A (ja) * 1982-09-28 1984-04-04 Toshiba Corp 半導体ウエ−ハ、半導体ウエ−ハの製造方法及び半導体ウエ−ハの製造装置
JPS59174514A (ja) * 1983-03-22 1984-10-03 Hoxan Corp 多結晶シリコンウエハの製造方法
JPS62132324A (ja) * 1985-12-04 1987-06-15 Showa Denko Kk ウエハ−の面取り研削ダメ−ジ層の除去方法および除去用治具
JPS63117427A (ja) * 1986-11-06 1988-05-21 Mitsubishi Electric Corp 半導体装置の製造方法
IT1229640B (it) * 1987-06-29 1991-09-04 S G S Microelettronica S P A O Processo di conformazione del bordo di fette di materiale semiconduttore e relativa apparecchiatura
JPH06103678B2 (ja) * 1987-11-28 1994-12-14 株式会社東芝 半導体基板の加工方法
US5128281A (en) * 1991-06-05 1992-07-07 Texas Instruments Incorporated Method for polishing semiconductor wafer edges

Also Published As

Publication number Publication date
DE69429122D1 (de) 2002-01-03
EP0607940A2 (de) 1994-07-27
EP0607940A3 (de) 1996-12-27
US5424224A (en) 1995-06-13
JPH06349796A (ja) 1994-12-22
EP0607940B1 (de) 2001-11-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee