DE69424666D1 - Schaltung zur taktruckgewinnung mit mehreren phasenregelschleifen - Google Patents
Schaltung zur taktruckgewinnung mit mehreren phasenregelschleifenInfo
- Publication number
- DE69424666D1 DE69424666D1 DE69424666T DE69424666T DE69424666D1 DE 69424666 D1 DE69424666 D1 DE 69424666D1 DE 69424666 T DE69424666 T DE 69424666T DE 69424666 T DE69424666 T DE 69424666T DE 69424666 D1 DE69424666 D1 DE 69424666D1
- Authority
- DE
- Germany
- Prior art keywords
- loopes
- circuit
- phase control
- clock recovery
- several phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000011084 recovery Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
- G11B20/1217—Formatting, e.g. arrangement of data block or words on the record carriers on discs
- G11B20/1258—Formatting, e.g. arrangement of data block or words on the record carriers on discs where blocks are arranged within multiple radial zones, e.g. Zone Bit Recording or Constant Density Recording discs, MCAV discs, MCLV discs
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/055,137 US5329251A (en) | 1993-04-28 | 1993-04-28 | Multiple biasing phase-lock-loops controlling center frequency of phase-lock-loop clock recovery circuit |
PCT/US1994/003974 WO1994026047A1 (en) | 1993-04-28 | 1994-04-12 | A multiple phase-lock-loop clock recovery circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69424666D1 true DE69424666D1 (de) | 2000-06-29 |
DE69424666T2 DE69424666T2 (de) | 2001-01-25 |
Family
ID=21995867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69424666T Expired - Lifetime DE69424666T2 (de) | 1993-04-28 | 1994-04-12 | Schaltung zur taktruckgewinnung mit mehreren phasenregelschleifen |
Country Status (6)
Country | Link |
---|---|
US (1) | US5329251A (de) |
EP (1) | EP0696396B1 (de) |
JP (1) | JP3379959B2 (de) |
KR (1) | KR100311445B1 (de) |
DE (1) | DE69424666T2 (de) |
WO (1) | WO1994026047A1 (de) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5625506A (en) * | 1994-06-17 | 1997-04-29 | International Business Machines Corporation | Method and apparatus for reducing readback errors by controlling the phase locked loop |
US5552942A (en) * | 1994-08-23 | 1996-09-03 | Quantum Corporation | Zero phase start optimization using mean squared error in a PRML recording channel |
US5414390A (en) * | 1994-09-12 | 1995-05-09 | Analog Devices, Inc. | Center frequency controlled phase locked loop system |
US5796535A (en) * | 1995-05-12 | 1998-08-18 | Cirrus Logic, Inc. | Sampled amplitude read channel employing a user data frequency synthesizer and a servo data frequency synthesizer |
US5999571A (en) * | 1995-10-05 | 1999-12-07 | Silicon Image, Inc. | Transition-controlled digital encoding and signal transmission system |
US5825824A (en) * | 1995-10-05 | 1998-10-20 | Silicon Image, Inc. | DC-balanced and transition-controlled encoding method and apparatus |
US5974464A (en) * | 1995-10-06 | 1999-10-26 | Silicon Image, Inc. | System for high speed serial video signal transmission using DC-balanced coding |
US5610558A (en) * | 1995-11-03 | 1997-03-11 | Motorola, Inc. | Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements |
US5790332A (en) * | 1995-11-07 | 1998-08-04 | Pc Peripherals Inc. | Method and apparatus for generating clock signals having count closure and deterministically optimized phase closure |
US5809397A (en) * | 1996-02-29 | 1998-09-15 | Motorola, Inc. | Method and apparatus for system synchronization in a messaging system |
US5703850A (en) * | 1996-06-18 | 1997-12-30 | Cirrus Logic, Inc. | Data retrieval system and method within a constant angular velocity CD-ROM |
WO1998048514A2 (en) * | 1997-04-24 | 1998-10-29 | Koninklijke Philips Electronics N.V. | Frequency synthesizer, particularly for use in a channel ic for hard disks |
TW501354B (en) * | 1999-05-25 | 2002-09-01 | Sony Corp | Digital signal processing device and method, digital signal processing system |
US7253047B2 (en) * | 1999-09-01 | 2007-08-07 | Micron Technology, Inc. | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry |
US7027525B2 (en) * | 1999-12-07 | 2006-04-11 | Josef Dirr | Digital transmission method for bandwidth and bit rate flexibility |
GB2363268B (en) * | 2000-06-08 | 2004-04-14 | Mitel Corp | Timing circuit with dual phase locked loops |
US7571359B2 (en) * | 2000-07-31 | 2009-08-04 | Massachusetts Institute Of Technology | Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals |
US6693987B1 (en) | 2000-10-05 | 2004-02-17 | Pericom Semiconductor Corp. | Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages |
US7010077B1 (en) * | 2000-11-20 | 2006-03-07 | Agere Systems Inc. | Gated clock recovery circuit |
JP4213359B2 (ja) * | 2001-05-11 | 2009-01-21 | 富士通マイクロエレクトロニクス株式会社 | 信号生成回路、タイミングリカバリpll,信号生成システム及び信号生成方法 |
GB2387494B (en) * | 2002-04-12 | 2005-02-09 | Nec Technologies | Mobile radio communications device and method of operation |
US7720448B2 (en) * | 2003-12-30 | 2010-05-18 | Freescale Semiconductor, Inc. | Signal generation power management control system for portable communications device and method of using same |
JP4628440B2 (ja) * | 2008-03-31 | 2011-02-09 | 富士通株式会社 | クロック発生機能付き装置、基準周波数等設定方法、および基準周波数等調整方法 |
US9379540B2 (en) * | 2010-12-23 | 2016-06-28 | Texas Instruments Incorporated | Controllable circuits, processes and systems for functional ESD tolerance |
WO2021121637A1 (en) | 2019-12-20 | 2021-06-24 | Telefonaktiebolaget Lm Ericsson (Publ) | Multiple pll system with common and difference mode loop filters |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4590602A (en) * | 1983-08-18 | 1986-05-20 | General Signal | Wide range clock recovery circuit |
US4980652A (en) * | 1988-09-02 | 1990-12-25 | Nippon Telegraph And Telephone Corporation | Frequency synthesizer having compensation for nonlinearities |
JPH02244820A (ja) * | 1989-03-16 | 1990-09-28 | Oki Electric Ind Co Ltd | Pll回路 |
US5072195A (en) * | 1990-04-05 | 1991-12-10 | Gazelle Microcircuits, Inc. | Phase-locked loop with clamped voltage-controlled oscillator |
US5043677A (en) * | 1990-06-29 | 1991-08-27 | Texas Instruments Incorporated | Time reference signal generation system |
US5170297A (en) * | 1990-07-13 | 1992-12-08 | Standard Microsystems Corporation | Current averaging data separator |
JPH0529932A (ja) * | 1991-07-24 | 1993-02-05 | Matsushita Electric Ind Co Ltd | クロツク切り換え装置 |
-
1993
- 1993-04-28 US US08/055,137 patent/US5329251A/en not_active Expired - Fee Related
-
1994
- 1994-04-12 WO PCT/US1994/003974 patent/WO1994026047A1/en active IP Right Grant
- 1994-04-12 DE DE69424666T patent/DE69424666T2/de not_active Expired - Lifetime
- 1994-04-12 EP EP94914120A patent/EP0696396B1/de not_active Expired - Lifetime
- 1994-04-12 KR KR1019950704676A patent/KR100311445B1/ko not_active IP Right Cessation
- 1994-04-12 JP JP52430394A patent/JP3379959B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5329251A (en) | 1994-07-12 |
EP0696396B1 (de) | 2000-05-24 |
DE69424666T2 (de) | 2001-01-25 |
JP3379959B2 (ja) | 2003-02-24 |
WO1994026047A1 (en) | 1994-11-10 |
JPH08510366A (ja) | 1996-10-29 |
EP0696396A1 (de) | 1996-02-14 |
KR960702233A (ko) | 1996-03-28 |
KR100311445B1 (ko) | 2001-12-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |