DE69332006D1 - Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen - Google Patents

Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen

Info

Publication number
DE69332006D1
DE69332006D1 DE69332006T DE69332006T DE69332006D1 DE 69332006 D1 DE69332006 D1 DE 69332006D1 DE 69332006 T DE69332006 T DE 69332006T DE 69332006 T DE69332006 T DE 69332006T DE 69332006 D1 DE69332006 D1 DE 69332006D1
Authority
DE
Germany
Prior art keywords
planar
procedure
alignment marks
common alignment
tub implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69332006T
Other languages
English (en)
Other versions
DE69332006T2 (de
Inventor
James Nmi Reynolds
Michael C Smayling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69332006D1 publication Critical patent/DE69332006D1/de
Publication of DE69332006T2 publication Critical patent/DE69332006T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Non-Volatile Memory (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
DE69332006T 1992-03-25 1993-03-02 Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen Expired - Fee Related DE69332006T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US85753392A 1992-03-25 1992-03-25

Publications (2)

Publication Number Publication Date
DE69332006D1 true DE69332006D1 (de) 2002-07-18
DE69332006T2 DE69332006T2 (de) 2002-11-28

Family

ID=25326214

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69332006T Expired - Fee Related DE69332006T2 (de) 1992-03-25 1993-03-02 Planares Verfahren unter Verwendung von gemeinsamen Ausrichtungsmarken für die Wannenimplantierungen

Country Status (6)

Country Link
US (1) US5500392A (de)
EP (1) EP0562309B1 (de)
JP (1) JPH0645535A (de)
KR (1) KR100318283B1 (de)
DE (1) DE69332006T2 (de)
TW (1) TW243545B (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4341171C2 (de) * 1993-12-02 1997-04-17 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung
DE19534784C1 (de) * 1995-09-19 1997-04-24 Siemens Ag Halbleiter-Schaltungselement und Verfahren zu seiner Herstellung
US5547894A (en) * 1995-12-21 1996-08-20 International Business Machines Corporation CMOS processing with low and high-current FETs
US6307273B1 (en) * 1996-06-07 2001-10-23 Vanguard International Semiconductor Corporation High contrast, low noise alignment mark for laser trimming of redundant memory arrays
JP3519571B2 (ja) * 1997-04-11 2004-04-19 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2982759B2 (ja) * 1997-08-12 1999-11-29 日本電気株式会社 半導体装置の製造方法
KR100268516B1 (ko) * 1998-03-02 2000-11-01 김규현 반도체소자의측정용패턴
US6124157A (en) * 1998-03-20 2000-09-26 Cypress Semiconductor Corp. Integrated non-volatile and random access memory and method of forming the same
US6207991B1 (en) 1998-03-20 2001-03-27 Cypress Semiconductor Corp. Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same
US6261932B1 (en) * 1999-07-29 2001-07-17 Fairchild Semiconductor Corp. Method of fabricating Schottky diode and related structure
US6683362B1 (en) 1999-08-24 2004-01-27 Kenneth K. O Metal-semiconductor diode clamped complementary field effect transistor integrated circuits
JP2003234423A (ja) * 2002-02-07 2003-08-22 Sony Corp 半導体装置及びその製造方法
FR2869459B1 (fr) * 2004-04-21 2006-08-04 Commissariat Energie Atomique Realignement entre niveaux apres une etape d'epitaxie.
TW200642695A (en) * 2005-03-08 2006-12-16 Genentech Inc Methods for identifying tumors responsive to treatment with her dimerization inhibitors (HDIs)
US7817265B2 (en) * 2008-09-25 2010-10-19 United Microelectronics Corp. Alignment mark and defect inspection method
TWI412068B (zh) * 2008-09-25 2013-10-11 United Microelectronics Corp 對準標記及缺陷檢測方法
US9054149B2 (en) * 2012-09-06 2015-06-09 Freescale Semiconductor, Inc. Semiconductor device with diagonal conduction path

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3697318A (en) * 1967-05-23 1972-10-10 Ibm Monolithic integrated structure including fabrication thereof
FR2282162A1 (fr) * 1974-08-12 1976-03-12 Radiotechnique Compelec Procede de realisation de dispositifs semiconducteurs
US4462151A (en) * 1982-12-03 1984-07-31 International Business Machines Corporation Method of making high density complementary transistors
WO1985005736A1 (en) * 1984-05-25 1985-12-19 American Microsystems, Inc. Tri-well cmos technology
JPH0722179B2 (ja) * 1985-12-27 1995-03-08 日本電気株式会社 半導体ウエ−ハの位置合せマ−クの形成方法
US4707455A (en) * 1986-11-26 1987-11-17 General Electric Company Method of fabricating a twin tub CMOS device
JPS63187628A (ja) * 1987-01-30 1988-08-03 Toshiba Corp 電子ビ−ム露光用位置合せマ−クの形成方法
US5059546A (en) * 1987-05-01 1991-10-22 Texas Instruments Incorporated BICMOS process for forming shallow NPN emitters and mosfet source/drains
JP2710935B2 (ja) * 1987-08-08 1998-02-10 三菱電機株式会社 半導体装置
US4936930A (en) * 1988-01-06 1990-06-26 Siliconix Incorporated Method for improved alignment for semiconductor devices with buried layers
US5043788A (en) * 1988-08-26 1991-08-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with functional portions having different operating voltages on one semiconductor substrate
JPH0824145B2 (ja) * 1988-12-19 1996-03-06 株式会社東芝 Ｃｍｏｓ半導体装置の製造方法
US5047358A (en) * 1989-03-17 1991-09-10 Delco Electronics Corporation Process for forming high and low voltage CMOS transistors on a single integrated circuit chip
JP2897248B2 (ja) * 1989-04-18 1999-05-31 富士通株式会社 半導体装置の製造方法
DE4214302C2 (de) * 1991-05-03 2000-01-13 Hyundai Electronics Ind Verfahren zur Herstellung einer CMOS-Struktur mit Doppelwannen
US5242841A (en) * 1992-03-25 1993-09-07 Texas Instruments Incorporated Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate

Also Published As

Publication number Publication date
US5500392A (en) 1996-03-19
JPH0645535A (ja) 1994-02-18
KR100318283B1 (ko) 2002-03-20
EP0562309A2 (de) 1993-09-29
EP0562309A3 (de) 1998-10-07
EP0562309B1 (de) 2002-06-12
TW243545B (de) 1995-03-21
DE69332006T2 (de) 2002-11-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee