DE69326312D1 - Herstellungsverfahren für eine Speicherzellanordnung hoher Dichte vom Typ Gain Cell - Google Patents

Herstellungsverfahren für eine Speicherzellanordnung hoher Dichte vom Typ Gain Cell

Info

Publication number
DE69326312D1
DE69326312D1 DE69326312T DE69326312T DE69326312D1 DE 69326312 D1 DE69326312 D1 DE 69326312D1 DE 69326312 T DE69326312 T DE 69326312T DE 69326312 T DE69326312 T DE 69326312T DE 69326312 D1 DE69326312 D1 DE 69326312D1
Authority
DE
Germany
Prior art keywords
forming
depositing
layer
gate
openings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69326312T
Other languages
English (en)
Other versions
DE69326312T2 (de
Inventor
Wolfgang Krautschneider
Werner Klingenstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE69326312D1 publication Critical patent/DE69326312D1/de
Publication of DE69326312T2 publication Critical patent/DE69326312T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69326312T 1992-12-16 1993-12-08 Herstellungsverfahren für eine Speicherzellanordnung hoher Dichte vom Typ Gain Cell Expired - Fee Related DE69326312T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/991,776 US5308783A (en) 1992-12-16 1992-12-16 Process for the manufacture of a high density cell array of gain memory cells

Publications (2)

Publication Number Publication Date
DE69326312D1 true DE69326312D1 (de) 1999-10-14
DE69326312T2 DE69326312T2 (de) 2000-02-17

Family

ID=25537551

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326312T Expired - Fee Related DE69326312T2 (de) 1992-12-16 1993-12-08 Herstellungsverfahren für eine Speicherzellanordnung hoher Dichte vom Typ Gain Cell

Country Status (7)

Country Link
US (1) US5308783A (de)
EP (1) EP0602525B1 (de)
JP (1) JP3495071B2 (de)
KR (1) KR100308076B1 (de)
AT (1) ATE184424T1 (de)
DE (1) DE69326312T2 (de)
HK (1) HK1003755A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960004079B1 (en) * 1992-12-19 1996-03-26 Lg Semicon Co Ltd Contact hole forming method
US5496771A (en) * 1994-05-19 1996-03-05 International Business Machines Corporation Method of making overpass mask/insulator for local interconnects
US5543348A (en) * 1995-03-29 1996-08-06 Kabushiki Kaisha Toshiba Controlled recrystallization of buried strap in a semiconductor memory device
EP0766312B1 (de) * 1995-09-26 2002-01-16 Infineon Technologies AG Selbstverstärkende DRAM-Speicherzellenanordnung
US5905279A (en) * 1996-04-09 1999-05-18 Kabushiki Kaisha Toshiba Low resistant trench fill for a semiconductor device
US6025220A (en) 1996-06-18 2000-02-15 Micron Technology, Inc. Method of forming a polysilicon diode and devices incorporating such diode
US5732014A (en) * 1997-02-20 1998-03-24 Micron Technology, Inc. Merged transistor structure for gain memory cell
US6436760B1 (en) * 2001-04-19 2002-08-20 International Business Machines Corporation Method for reducing surface oxide in polysilicon processing
US6979651B1 (en) * 2002-07-29 2005-12-27 Advanced Micro Devices, Inc. Method for forming alignment features and back-side contacts with fewer lithography and etch steps
US7224024B2 (en) * 2002-08-29 2007-05-29 Micron Technology, Inc. Single transistor vertical memory gain cell
US6838723B2 (en) * 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US20040061190A1 (en) * 2002-09-30 2004-04-01 International Business Machines Corporation Method and structure for tungsten gate metal surface treatment while preventing oxidation
US6804142B2 (en) * 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US7030436B2 (en) * 2002-12-04 2006-04-18 Micron Technology, Inc. Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means
US6956256B2 (en) * 2003-03-04 2005-10-18 Micron Technology Inc. Vertical gain cell
US8583213B2 (en) * 2006-09-12 2013-11-12 General Electric Company Combined MR imaging and tracking
US9359865B2 (en) 2012-10-15 2016-06-07 Baker Hughes Incorporated Pressure actuated ported sub for subterranean cement completions
US20160064285A1 (en) * 2013-03-27 2016-03-03 Ps4 Luxco S.A.R.L.) Manufacturing method for semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2070329B (en) * 1980-01-25 1983-10-26 Tokyo Shibaura Electric Co Semiconductor memory device
US4543595A (en) * 1982-05-20 1985-09-24 Fairchild Camera And Instrument Corporation Bipolar memory cell
US4416404A (en) * 1983-01-26 1983-11-22 Daniels Fitz A S C Belt type garment for carrying tennis balls and the like
JPS604253A (ja) * 1983-06-23 1985-01-10 Nec Corp 半導体集積回路メモリ
US4654825A (en) * 1984-01-06 1987-03-31 Advanced Micro Devices, Inc. E2 prom memory cell
CA1322250C (en) * 1987-08-31 1993-09-14 Loren Thomas Lancaster Active dynamic memory cell
JPH01145850A (ja) * 1987-12-02 1989-06-07 Oki Electric Ind Co Ltd 半導体記憶装置
US4914740A (en) * 1988-03-07 1990-04-03 International Business Corporation Charge amplifying trench memory cell
JPH01255269A (ja) * 1988-04-05 1989-10-12 Oki Electric Ind Co Ltd 半導体記憶装置
US5021849A (en) * 1989-10-30 1991-06-04 Motorola, Inc. Compact SRAM cell with polycrystalline silicon diode load
GB2238427A (en) * 1989-11-24 1991-05-29 Philips Electronic Associated Thin film diode devices and active matrix addressed display devices incorporating such

Also Published As

Publication number Publication date
JP3495071B2 (ja) 2004-02-09
KR100308076B1 (ko) 2001-12-15
ATE184424T1 (de) 1999-09-15
US5308783A (en) 1994-05-03
DE69326312T2 (de) 2000-02-17
KR940016777A (ko) 1994-07-25
EP0602525A1 (de) 1994-06-22
HK1003755A1 (en) 1998-11-06
JPH06216330A (ja) 1994-08-05
EP0602525B1 (de) 1999-09-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee