DE69325505T2 - Programmierungsverfahren einer EEPROM-Zelle mit doppelter Polysiliziumschicht - Google Patents

Programmierungsverfahren einer EEPROM-Zelle mit doppelter Polysiliziumschicht

Info

Publication number
DE69325505T2
DE69325505T2 DE69325505T DE69325505T DE69325505T2 DE 69325505 T2 DE69325505 T2 DE 69325505T2 DE 69325505 T DE69325505 T DE 69325505T DE 69325505 T DE69325505 T DE 69325505T DE 69325505 T2 DE69325505 T2 DE 69325505T2
Authority
DE
Germany
Prior art keywords
polysilicon layer
programming method
eeprom cell
double polysilicon
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69325505T
Other languages
English (en)
Other versions
DE69325505D1 (de
Inventor
Federico Pio
Carlo Riva
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69325505D1 publication Critical patent/DE69325505D1/de
Publication of DE69325505T2 publication Critical patent/DE69325505T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69325505T 1993-02-19 1993-02-19 Programmierungsverfahren einer EEPROM-Zelle mit doppelter Polysiliziumschicht Expired - Fee Related DE69325505T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93830061A EP0612107B1 (de) 1993-02-19 1993-02-19 Programmierungsverfahren einer EEPROM-Zelle mit doppelter Polysiliziumschicht

Publications (2)

Publication Number Publication Date
DE69325505D1 DE69325505D1 (de) 1999-08-05
DE69325505T2 true DE69325505T2 (de) 1999-10-28

Family

ID=8215121

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69325505T Expired - Fee Related DE69325505T2 (de) 1993-02-19 1993-02-19 Programmierungsverfahren einer EEPROM-Zelle mit doppelter Polysiliziumschicht

Country Status (2)

Country Link
EP (1) EP0612107B1 (de)
DE (1) DE69325505T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3200497B2 (ja) * 1993-03-19 2001-08-20 三菱電機株式会社 電気的に情報の書込および消去が可能な半導体記憶装置およびその製造方法
KR100413652B1 (ko) * 1995-09-11 2004-05-27 마츠시타 덴끼 산교 가부시키가이샤 반도체기억장치및그구동방법
EP1071134A1 (de) 1999-07-22 2001-01-24 STMicroelectronics S.r.l. Verfahren zur Herstellung eines Halbleiterbauelementes mit EEPROM-Speicherzellen unter Kontrolle der Abmessungen der Floating-Gate-Gebiete
US6617637B1 (en) * 2002-11-13 2003-09-09 Ememory Technology Inc. Electrically erasable programmable logic device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479203A (en) * 1981-11-16 1984-10-23 Motorola, Inc. Electrically erasable programmable read only memory cell
US4742492A (en) * 1985-09-27 1988-05-03 Texas Instruments Incorporated EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor
US4852062A (en) * 1987-09-28 1989-07-25 Motorola, Inc. EPROM device using asymmetrical transistor characteristics
JP2645122B2 (ja) * 1989-01-20 1997-08-25 株式会社東芝 不揮発性半導体メモリ
US5081054A (en) * 1989-04-03 1992-01-14 Atmel Corporation Fabrication process for programmable and erasable MOS memory device

Also Published As

Publication number Publication date
EP0612107B1 (de) 1999-06-30
EP0612107A1 (de) 1994-08-24
DE69325505D1 (de) 1999-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee