DE69323859T2 - Verfahren zur Herstellung einer isolierten Schicht - Google Patents

Verfahren zur Herstellung einer isolierten Schicht

Info

Publication number
DE69323859T2
DE69323859T2 DE69323859T DE69323859T DE69323859T2 DE 69323859 T2 DE69323859 T2 DE 69323859T2 DE 69323859 T DE69323859 T DE 69323859T DE 69323859 T DE69323859 T DE 69323859T DE 69323859 T2 DE69323859 T2 DE 69323859T2
Authority
DE
Germany
Prior art keywords
producing
isolated layer
isolated
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69323859T
Other languages
English (en)
Other versions
DE69323859D1 (de
Inventor
Shinji - Midori-Cho Yamada
Masaharu Shirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69323859D1 publication Critical patent/DE69323859D1/de
Publication of DE69323859T2 publication Critical patent/DE69323859T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0783—Using solvent, e.g. for cleaning; Regulating solvent content of pastes or coatings for adjusting the viscosity
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Formation Of Insulating Films (AREA)
DE69323859T 1993-01-18 1993-12-20 Verfahren zur Herstellung einer isolierten Schicht Expired - Fee Related DE69323859T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5005713A JP2925103B2 (ja) 1993-01-18 1993-01-18 表面平滑な絶縁層の形成方法

Publications (2)

Publication Number Publication Date
DE69323859D1 DE69323859D1 (de) 1999-04-15
DE69323859T2 true DE69323859T2 (de) 1999-10-07

Family

ID=11618765

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69323859T Expired - Fee Related DE69323859T2 (de) 1993-01-18 1993-12-20 Verfahren zur Herstellung einer isolierten Schicht

Country Status (4)

Country Link
US (1) US5460858A (de)
EP (1) EP0607691B1 (de)
JP (1) JP2925103B2 (de)
DE (1) DE69323859T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3442200B2 (ja) * 1995-08-08 2003-09-02 インターナショナル・ビジネス・マシーンズ・コーポレーション プリント回路基板、プリント回路基板の製造方法
JP2003037352A (ja) * 2001-07-25 2003-02-07 Nitto Denko Corp 配線回路基板の製造方法
WO2010053125A1 (ja) 2008-11-05 2010-05-14 株式会社 東芝 成膜装置、成膜方法及び半導体装置
JP4748742B2 (ja) * 2009-02-13 2011-08-17 東京エレクトロン株式会社 基板処理装置及び基板処理方法
TWI730037B (zh) * 2016-01-26 2021-06-11 日商富士軟片和光純藥股份有限公司 光硬化方法，及用於該光硬化方法之化合物和組成物

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3529960A (en) * 1967-01-24 1970-09-22 Hilbert Sloan Methods of treating resist coatings
US3684553A (en) * 1970-12-14 1972-08-15 Du Pont Process for removing surface defects from articles having a thermoplastic surface
JPS6386434A (ja) * 1986-09-30 1988-04-16 Toshiba Corp レジストパタ−ン形成方法
US4794021A (en) * 1986-11-13 1988-12-27 Microelectronics And Computer Technology Corporation Method of providing a planarized polymer coating on a substrate wafer
JPH03184323A (ja) * 1989-12-13 1991-08-12 Mitsubishi Electric Corp 高段差基板上の高精度レジストパターン形成方法

Also Published As

Publication number Publication date
JP2925103B2 (ja) 1999-07-28
US5460858A (en) 1995-10-24
EP0607691B1 (de) 1999-03-10
JPH06236871A (ja) 1994-08-23
EP0607691A2 (de) 1994-07-27
DE69323859D1 (de) 1999-04-15
EP0607691A3 (de) 1997-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee