DE69312676D1 - Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz - Google Patents

Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz

Info

Publication number
DE69312676D1
DE69312676D1 DE69312676T DE69312676T DE69312676D1 DE 69312676 D1 DE69312676 D1 DE 69312676D1 DE 69312676 T DE69312676 T DE 69312676T DE 69312676 T DE69312676 T DE 69312676T DE 69312676 D1 DE69312676 D1 DE 69312676D1
Authority
DE
Germany
Prior art keywords
diodes
layer
transistors
active areas
poly2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69312676T
Other languages
English (en)
Other versions
DE69312676T2 (de
Inventor
Paolo Giuseppe Cappelletti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE69312676D1 publication Critical patent/DE69312676D1/de
Publication of DE69312676T2 publication Critical patent/DE69312676T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/979—Tunnel diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69312676T 1993-02-17 1993-02-17 Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz Expired - Fee Related DE69312676T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93830057A EP0613176B1 (de) 1993-02-17 1993-02-17 Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz

Publications (2)

Publication Number Publication Date
DE69312676D1 true DE69312676D1 (de) 1997-09-04
DE69312676T2 DE69312676T2 (de) 1997-12-04

Family

ID=8215118

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69312676T Expired - Fee Related DE69312676T2 (de) 1993-02-17 1993-02-17 Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz

Country Status (4)

Country Link
US (2) US5466622A (de)
EP (1) EP0613176B1 (de)
JP (1) JP3606596B2 (de)
DE (1) DE69312676T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0613176B1 (de) * 1993-02-17 1997-07-30 STMicroelectronics S.r.l. Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz
US5556798A (en) * 1994-12-01 1996-09-17 United Microelectronics Corp. Method for isolating non-volatile memory cells
US5576234A (en) * 1995-11-13 1996-11-19 Hualon Microelectronics Corporation Method for manufacturing an EPROM
US5851882A (en) * 1996-05-06 1998-12-22 Micron Technology, Inc. ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask
JP3545131B2 (ja) * 1996-06-11 2004-07-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5716880A (en) * 1997-02-20 1998-02-10 Chartered Semiconductor Manufacturing Pte Ltd. Method for forming vertical polysilicon diode compatible with CMOS/BICMOS formation
JP3586072B2 (ja) * 1997-07-10 2004-11-10 株式会社東芝 不揮発性半導体記憶装置
JP3221369B2 (ja) 1997-09-19 2001-10-22 日本電気株式会社 不揮発性半導体記憶装置及びその製造方法
US6020237A (en) * 1998-02-04 2000-02-01 Alliance Semiconductor Corporation Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures
JP3228230B2 (ja) * 1998-07-21 2001-11-12 日本電気株式会社 半導体装置の製造方法
US6096573A (en) * 1998-11-05 2000-08-01 United Microelectronics Corp. Method of manufacturing a CMOS sensor
US6143608A (en) * 1999-03-31 2000-11-07 Advanced Micro Devices, Inc. Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation
EP1071134A1 (de) * 1999-07-22 2001-01-24 STMicroelectronics S.r.l. Verfahren zur Herstellung eines Halbleiterbauelementes mit EEPROM-Speicherzellen unter Kontrolle der Abmessungen der Floating-Gate-Gebiete
US6277723B1 (en) 1999-10-14 2001-08-21 Taiwan Semiconductor Manufacturing Company Plasma damage protection cell using floating N/P/N and P/N/P structure
DE10207122B4 (de) * 2002-02-20 2007-07-05 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zur Herstellung von Schichten aus Oxid auf einer Oberfläche eines Substrats
US7196369B2 (en) * 2002-07-15 2007-03-27 Macronix International Co., Ltd. Plasma damage protection circuit for a semiconductor device
ITMI20022467A1 (it) * 2002-11-20 2004-05-21 St Microelectronics Srl Processo per realizzare un transistore di selezione di byte per
US6900097B2 (en) * 2003-05-12 2005-05-31 United Microelectronics Corp. Method for forming single-level electrically erasable and programmable read only memory operated in environment with high/low-voltage
US6869844B1 (en) * 2003-11-05 2005-03-22 Advanced Micro Device, Inc. Method and structure for protecting NROM devices from induced charge damage during device fabrication
US7170816B2 (en) * 2004-12-16 2007-01-30 Macronix International Co., Ltd. Method and apparatus for passing charge from word lines during manufacture
US8651062B2 (en) 2010-12-10 2014-02-18 Marc H. Arsenault Easy to insert pet carrier
CN104425366B (zh) * 2013-08-20 2017-12-29 中芯国际集成电路制造(北京)有限公司 半导体结构的形成方法
US9490249B2 (en) 2014-04-30 2016-11-08 Macronix International Co., Ltd. Antenna effect discharge circuit and manufacturing method
US10868027B2 (en) 2018-07-13 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for preventing silicide contamination during the manufacture of micro-processors with embedded flash memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213249B (it) * 1984-11-26 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.
US4635347A (en) * 1985-03-29 1987-01-13 Advanced Micro Devices, Inc. Method of fabricating titanium silicide gate electrodes and interconnections
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor
EP0613176B1 (de) * 1993-02-17 1997-07-30 STMicroelectronics S.r.l. Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz

Also Published As

Publication number Publication date
US5466622A (en) 1995-11-14
EP0613176A1 (de) 1994-08-31
DE69312676T2 (de) 1997-12-04
JP3606596B2 (ja) 2005-01-05
EP0613176B1 (de) 1997-07-30
JPH0745729A (ja) 1995-02-14
US5913120A (en) 1999-06-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee