DE69225040D1 - CMOS-pseudo-NMOS programmierbares Kapazitäts-Zeitvernierssystem und Verfahren zur gesteuerten Verzögerung von Zeitflanken - Google Patents

CMOS-pseudo-NMOS programmierbares Kapazitäts-Zeitvernierssystem und Verfahren zur gesteuerten Verzögerung von Zeitflanken

Info

Publication number
DE69225040D1
DE69225040D1 DE69225040T DE69225040T DE69225040D1 DE 69225040 D1 DE69225040 D1 DE 69225040D1 DE 69225040 T DE69225040 T DE 69225040T DE 69225040 T DE69225040 T DE 69225040T DE 69225040 D1 DE69225040 D1 DE 69225040D1
Authority
DE
Germany
Prior art keywords
nmos
cmos
pseudo
timing system
controlled delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69225040T
Other languages
English (en)
Other versions
DE69225040T2 (de
Inventor
Christopher Koerner
Albert Gutierrez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/786,459 external-priority patent/US5243227A/en
Priority claimed from US07/786,633 external-priority patent/US5283631A/en
Priority claimed from US07/786,690 external-priority patent/US5233637A/en
Priority claimed from US07/786,447 external-priority patent/US5214680A/en
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69225040D1 publication Critical patent/DE69225040D1/de
Publication of DE69225040T2 publication Critical patent/DE69225040T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
    • G01R31/2841—Signal generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/687—Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/745—Simultaneous conversion using current sources as quantisation value generators with weighted currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
DE1992625040 1991-11-01 1992-10-19 CMOS-pseudo-NMOS programmierbares Kapazitäts-Zeitvernierssystem und Verfahren zur gesteuerten Verzögerung von Zeitflanken Expired - Fee Related DE69225040T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US78669591A 1991-11-01 1991-11-01
US07/786,459 US5243227A (en) 1991-11-01 1991-11-01 Fine/coarse wired-or tapped delay line
US07/786,633 US5283631A (en) 1991-11-01 1991-11-01 Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
US07/786,690 US5233637A (en) 1991-11-01 1991-11-01 System for generating an analog regulating voltage
US07/786,447 US5214680A (en) 1991-11-01 1991-11-01 CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration

Publications (2)

Publication Number Publication Date
DE69225040D1 true DE69225040D1 (de) 1998-05-14
DE69225040T2 DE69225040T2 (de) 1998-11-19

Family

ID=27542208

Family Applications (5)

Application Number Title Priority Date Filing Date
DE1992625040 Expired - Fee Related DE69225040T2 (de) 1991-11-01 1992-10-19 CMOS-pseudo-NMOS programmierbares Kapazitäts-Zeitvernierssystem und Verfahren zur gesteuerten Verzögerung von Zeitflanken
DE1992631609 Expired - Fee Related DE69231609T2 (de) 1991-11-01 1992-10-19 Verdrahteter Oder-Multiplexer
DE1992625767 Expired - Fee Related DE69225767T2 (de) 1991-11-01 1992-10-19 Programmierbares Kapazitätsverzögerungselement in Pseudo-NMOS-Technik
DE1992625670 Expired - Fee Related DE69225670T2 (de) 1991-11-01 1992-10-19 Pseudo-NMOS grob/fein festverdrahtete oder mit Anzapfungen versehene Laufzeitleitung
DE1992627884 Expired - Fee Related DE69227884T2 (de) 1991-11-01 1992-10-19 Breitenveränderliches Stromspiegel-Digital/Analogsystem und Verfahren zur Generierung einer Steuerspannung zur Verzögerungserzeugung

Family Applications After (4)

Application Number Title Priority Date Filing Date
DE1992631609 Expired - Fee Related DE69231609T2 (de) 1991-11-01 1992-10-19 Verdrahteter Oder-Multiplexer
DE1992625767 Expired - Fee Related DE69225767T2 (de) 1991-11-01 1992-10-19 Programmierbares Kapazitätsverzögerungselement in Pseudo-NMOS-Technik
DE1992625670 Expired - Fee Related DE69225670T2 (de) 1991-11-01 1992-10-19 Pseudo-NMOS grob/fein festverdrahtete oder mit Anzapfungen versehene Laufzeitleitung
DE1992627884 Expired - Fee Related DE69227884T2 (de) 1991-11-01 1992-10-19 Breitenveränderliches Stromspiegel-Digital/Analogsystem und Verfahren zur Generierung einer Steuerspannung zur Verzögerungserzeugung

Country Status (3)

Country Link
EP (6) EP0539832B1 (de)
JP (5) JP3382647B2 (de)
DE (5) DE69225040T2 (de)

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FR2696061B1 (fr) * 1992-09-22 1994-12-02 Rainard Jean Luc Procédé pour retarder temporellement un signal et circuit à retard correspondant.
GB9322920D0 (en) * 1993-11-06 1993-12-22 Bicc Plc Device for testing an electrical line
WO1997024806A1 (en) * 1995-12-28 1997-07-10 Advantest Corporation Semiconductor integrated circuit device with delay error correcting circuit
US5963074A (en) * 1997-06-18 1999-10-05 Credence Systems Corporation Programmable delay circuit having calibratable delays
JP3560780B2 (ja) * 1997-07-29 2004-09-02 富士通株式会社 可変遅延回路及び半導体集積回路装置
JP2908398B1 (ja) 1998-01-14 1999-06-21 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路および発振器の遅延素子
EP0967727A1 (de) * 1998-06-23 1999-12-29 Lucent Technologies Inc. Verfahren und elektronische Schaltung zur Bereitstellung eines stabilen analogen Ausgangssignals in einem integrierten Digital-Analog-Wandler
JP3430046B2 (ja) 1998-12-17 2003-07-28 エヌイーシーマイクロシステム株式会社 リング発振器
FR2792474B1 (fr) * 1999-04-13 2001-06-29 St Microelectronics Sa Circuit de sortie de signal numerique
DE10038372C2 (de) 2000-08-07 2003-03-13 Infineon Technologies Ag Differentieller Digital/Analog-Wandler
DE10164822B4 (de) * 2000-08-29 2007-04-12 Advantest Corp. Prüfvorrichtung
JP4508385B2 (ja) * 2000-08-31 2010-07-21 株式会社アドバンテスト タイミング発生器及び半導体試験装置
DE10147121B4 (de) * 2000-09-29 2004-06-17 Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto Schaltung zum Aufteilen der Fein- und Grob-Verzögerungssteuerung von Verzögerungsleitungen zur Verwendung beim Laden von Verzögerungsdaten
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit
JP4670675B2 (ja) 2006-02-16 2011-04-13 ソニー株式会社 電荷転送部の駆動回路及び電荷転送部の駆動方法
WO2011041060A2 (en) * 2009-09-30 2011-04-07 Rambus Inc. Methods and systems for reducing supply and termination noise in programmable delay lines
CN101924561B (zh) * 2010-07-02 2013-06-19 清华大学 用于电流型数模转换器中电流源导通阵列及其构造方法
US20140103985A1 (en) * 2012-10-11 2014-04-17 Easic Corporation Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
US9024657B2 (en) 2012-10-11 2015-05-05 Easic Corporation Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller
CN103368576B (zh) * 2013-07-15 2016-05-18 北京时代民芯科技有限公司 一种数字控制数模转换器满偏输出电流的方法
US10090881B2 (en) 2015-11-13 2018-10-02 Renesas Electronics Corporation Semiconductor device
JP2021052258A (ja) * 2019-09-24 2021-04-01 セイコーエプソン株式会社 回路装置、物理量測定装置、電子機器及び移動体
CN110703582B (zh) * 2019-09-25 2021-02-26 天津大学 用于时间数字转换器的温度计码转二进制码电路

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US3502994A (en) * 1966-11-02 1970-03-24 Data Control Systems Inc Electrically variable delay line
NL165896C (nl) * 1974-07-05 1981-05-15 Matsushita Electric Ind Co Ltd Spanningsleveringsinrichting.
US4045793A (en) * 1975-09-29 1977-08-30 Motorola, Inc. Digital to analog converter
US4064506A (en) * 1976-04-08 1977-12-20 Rca Corporation Current mirror amplifiers with programmable current gains
US4330750A (en) * 1979-03-13 1982-05-18 International Computers Limited Variable delay circuits
DE2914108C2 (de) * 1979-04-07 1984-03-08 Deutsche Itt Industries Gmbh, 7800 Freiburg Monolithisch integrierte Schaltungsanordnung für einen Digital-Analog-Wandler
US4384274A (en) * 1979-06-22 1983-05-17 American Microsystems, Inc. Current mirror digital to analog converter
EP0074859A2 (de) * 1981-09-16 1983-03-23 Brooktree Corporation Digital-Analog-Wandler
US4431986A (en) * 1981-10-09 1984-02-14 American Microsystems, Incorporated Digital to analog and analog to digital converters with bipolar output signals
JPS58184821A (ja) * 1982-03-31 1983-10-28 Fujitsu Ltd 昇圧回路
CA1204171A (en) * 1983-07-15 1986-05-06 Stephen K. Sunter Programmable logic array
JPS6089775A (ja) * 1983-08-01 1985-05-20 フエアチアイルド　カメラ　アンド　インストルメント　コ−ポレ−シヨン 自動テスト装置用のテスト期間発生器
EP0135274A3 (de) * 1983-08-12 1987-12-16 Trw Inc. Digital-Analog-Umsetzer
DE3511625A1 (de) * 1985-03-29 1986-10-02 Siemens AG, 1000 Berlin und 8000 München Verdrahtete oder-anordnung
JPS6439827A (en) * 1987-08-05 1989-02-10 Mitsubishi Electric Corp Programmable logic array circuit
GB8728495D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Variable digital delay
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US5081380A (en) * 1989-10-16 1992-01-14 Advanced Micro Devices, Inc. Temperature self-compensated time delay circuits
US5012126A (en) * 1990-06-04 1991-04-30 Motorola, Inc. High speed CMOS multiplexer having reduced propagation delay
US5001482A (en) * 1990-06-11 1991-03-19 International Business Machines Corporation BiCMOS digital-to-analog converter for disk drive digital recording channel architecture

Also Published As

Publication number Publication date
DE69225670T2 (de) 1999-01-21
EP0539828A3 (de) 1995-08-09
DE69227884T2 (de) 1999-07-29
DE69227884D1 (de) 1999-01-28
DE69225040T2 (de) 1998-11-19
DE69225767D1 (de) 1998-07-09
EP0539828A2 (de) 1993-05-05
EP0792019A1 (de) 1997-08-27
JP3357098B2 (ja) 2002-12-16
EP0539830B1 (de) 1998-05-27
DE69225767T2 (de) 1999-01-14
EP0539831A2 (de) 1993-05-05
EP0539831B1 (de) 1998-06-03
EP0539830A2 (de) 1993-05-05
JPH05259844A (ja) 1993-10-08
EP0539831A3 (de) 1995-04-26
DE69231609D1 (de) 2001-01-25
DE69225670D1 (de) 1998-07-02
EP0539832A3 (de) 1995-04-19
JPH05259908A (ja) 1993-10-08
JPH05268014A (ja) 1993-10-15
JPH05259845A (ja) 1993-10-08
EP0793345A1 (de) 1997-09-03
EP0539828B1 (de) 1998-12-16
JPH05259843A (ja) 1993-10-08
JP3382647B2 (ja) 2003-03-04
EP0792019B1 (de) 2000-12-20
EP0539832A2 (de) 1993-05-05
EP0539832B1 (de) 1998-04-08
EP0539830A3 (de) 1995-08-09
DE69231609T2 (de) 2001-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee