DE69222794D1 - Vorspannungs-Erzeugungsschaltung für ECL-Pegel mit Verringerung des Leistungsverbrauchs derselben - Google Patents

Vorspannungs-Erzeugungsschaltung für ECL-Pegel mit Verringerung des Leistungsverbrauchs derselben

Info

Publication number
DE69222794D1
DE69222794D1 DE69222794T DE69222794T DE69222794D1 DE 69222794 D1 DE69222794 D1 DE 69222794D1 DE 69222794 T DE69222794 T DE 69222794T DE 69222794 T DE69222794 T DE 69222794T DE 69222794 D1 DE69222794 D1 DE 69222794D1
Authority
DE
Germany
Prior art keywords
reduction
power consumption
generating circuit
bias generating
ecl levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69222794T
Other languages
English (en)
Other versions
DE69222794T2 (de
Inventor
Kazuyuki Nonaka
Tetsuya Aisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Application granted granted Critical
Publication of DE69222794D1 publication Critical patent/DE69222794D1/de
Publication of DE69222794T2 publication Critical patent/DE69222794T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE69222794T 1991-03-13 1992-03-10 Vorspannungs-Erzeugungsschaltung für ECL-Pegel mit Verringerung des Leistungsverbrauchs derselben Expired - Fee Related DE69222794T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3048205A JP3001014B2 (ja) 1991-03-13 1991-03-13 バイアス電圧発生回路

Publications (2)

Publication Number Publication Date
DE69222794D1 true DE69222794D1 (de) 1997-11-27
DE69222794T2 DE69222794T2 (de) 1998-02-19

Family

ID=12796888

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69222794T Expired - Fee Related DE69222794T2 (de) 1991-03-13 1992-03-10 Vorspannungs-Erzeugungsschaltung für ECL-Pegel mit Verringerung des Leistungsverbrauchs derselben

Country Status (5)

Country Link
US (1) US5218238A (de)
EP (1) EP0503888B1 (de)
JP (1) JP3001014B2 (de)
KR (1) KR950006350B1 (de)
DE (1) DE69222794T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461338A (en) * 1992-04-17 1995-10-24 Nec Corporation Semiconductor integrated circuit incorporated with substrate bias control circuit
JP3318365B2 (ja) * 1992-10-20 2002-08-26 富士通株式会社 定電圧回路
US5357148A (en) * 1992-12-29 1994-10-18 Sgs-Thomson Microelectronics, Inc. Device for biasing an RF device operating in quasi-linear modes with voltage compensation
JP3304539B2 (ja) 1993-08-31 2002-07-22 富士通株式会社 基準電圧発生回路
FR2721772B1 (fr) * 1994-06-27 1996-09-06 Sgs Thomson Microelectronics Circuit de commande d'une source de polarisation comportant un dispositif de mise en veille.
FR2721771B1 (fr) * 1994-06-27 1996-09-06 Sgs Thomson Microelectronics Dispositif de mise en veille d'une source de polarisation.
JP3695606B2 (ja) * 1996-04-01 2005-09-14 忠弘 大見 半導体装置及びその製造方法
JP2000119181A (ja) 1998-10-06 2000-04-25 Kureha Chem Ind Co Ltd エスクレチン及びその誘導体の放出制御経口製剤
US6300752B1 (en) * 1999-05-24 2001-10-09 Level One Communications, Inc. Common mode bias voltage generator
US6531909B1 (en) 1999-09-15 2003-03-11 Linear Technology Corporation Load-generated drive, substantially no quiescent current, techniques and circuits for high speed switching of transistors
US7173474B1 (en) 1999-09-15 2007-02-06 Linear Technology Corporation Load-generated drive, no quiescent current, techniques and circuits for high speed switching of transistors
KR100430344B1 (ko) * 2002-03-22 2004-05-04 주식회사 케이이씨 바이어스 회로
US6870390B1 (en) * 2003-09-11 2005-03-22 Xilinx, Inc. Tx line driver with common mode idle state and selectable slew rates
US7187206B2 (en) 2003-10-30 2007-03-06 International Business Machines Corporation Power savings in serial link transmitters
JP2005227390A (ja) * 2004-02-10 2005-08-25 Sharp Corp 表示装置のドライバ回路および表示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3852119A (en) * 1972-11-14 1974-12-03 Texas Instruments Inc Metal-insulator-semiconductor structures having reduced junction capacitance and method of fabrication
JPS60176121A (ja) * 1984-02-22 1985-09-10 Toshiba Corp 電圧降下回路
US4639661A (en) * 1985-09-03 1987-01-27 Advanced Micro Devices, Inc. Power-down arrangement for an ECL circuit
JPS62197987A (ja) * 1986-02-24 1987-09-01 Mitsubishi Electric Corp 半導体記憶装置
US4713560A (en) * 1986-06-05 1987-12-15 Fairchild Semiconductor Corporation Switched impedance emitter coupled logic gate
JPS6474823A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Emitter follower circuit
US5023479A (en) * 1990-07-31 1991-06-11 Motorola, Inc. Low power output gate

Also Published As

Publication number Publication date
EP0503888A1 (de) 1992-09-16
JPH04284022A (ja) 1992-10-08
DE69222794T2 (de) 1998-02-19
KR920019085A (ko) 1992-10-22
EP0503888B1 (de) 1997-10-22
JP3001014B2 (ja) 2000-01-17
US5218238A (en) 1993-06-08
KR950006350B1 (ko) 1995-06-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee