DE69220398T2 - Plasma-Ätzverfahren einer Silizium enthaltenden Schicht - Google Patents

Plasma-Ätzverfahren einer Silizium enthaltenden Schicht

Info

Publication number
DE69220398T2
DE69220398T2 DE69220398T DE69220398T DE69220398T2 DE 69220398 T2 DE69220398 T2 DE 69220398T2 DE 69220398 T DE69220398 T DE 69220398T DE 69220398 T DE69220398 T DE 69220398T DE 69220398 T2 DE69220398 T2 DE 69220398T2
Authority
DE
Germany
Prior art keywords
etching process
layer containing
plasma etching
containing silicon
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69220398T
Other languages
English (en)
Other versions
DE69220398D1 (de
Inventor
Fumihiko Higuchi
Yoshio Fukasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of DE69220398D1 publication Critical patent/DE69220398D1/de
Application granted granted Critical
Publication of DE69220398T2 publication Critical patent/DE69220398T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
DE69220398T 1991-03-19 1992-03-13 Plasma-Ätzverfahren einer Silizium enthaltenden Schicht Expired - Fee Related DE69220398T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3078317A JP2920848B2 (ja) 1991-03-19 1991-03-19 シリコン層のエッチング方法

Publications (2)

Publication Number Publication Date
DE69220398D1 DE69220398D1 (de) 1997-07-24
DE69220398T2 true DE69220398T2 (de) 1997-11-06

Family

ID=13658565

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220398T Expired - Fee Related DE69220398T2 (de) 1991-03-19 1992-03-13 Plasma-Ätzverfahren einer Silizium enthaltenden Schicht

Country Status (5)

Country Link
EP (1) EP0504758B1 (de)
JP (1) JP2920848B2 (de)
KR (1) KR0175073B1 (de)
DE (1) DE69220398T2 (de)
TW (1) TW201847B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6165375A (en) 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
TW455948B (en) * 1999-09-13 2001-09-21 Motorola Inc Process for etching an insulating layer and forming a semiconductor device
US6794294B1 (en) * 1999-11-09 2004-09-21 Koninklijke Philips Electronics N.V. Etch process that resists notching at electrode bottom
US8679982B2 (en) * 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
JP7178918B2 (ja) * 2019-01-30 2022-11-28 東京エレクトロン株式会社 エッチング方法、プラズマ処理装置、及び処理システム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4431477A (en) * 1983-07-05 1984-02-14 Matheson Gas Products, Inc. Plasma etching with nitrous oxide and fluoro compound gas mixture
US4502915B1 (en) * 1984-01-23 1998-11-03 Texas Instruments Inc Two-step plasma process for selective anisotropic etching of polycrystalline silicon without leaving residue
US4726879A (en) * 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
EP0565212A2 (de) * 1986-12-19 1993-10-13 Applied Materials, Inc. Iodine-Ätzverfahren für Silizium und Silizide
DE68928977T2 (de) * 1988-02-09 1999-08-19 Fujitsu Ltd Trockenätzen mit Wasserstoffbromid oder Brom
US5007982A (en) * 1988-07-11 1991-04-16 North American Philips Corporation Reactive ion etching of silicon with hydrogen bromide
JP3004699B2 (ja) * 1990-09-07 2000-01-31 東京エレクトロン株式会社 プラズマ処理方法

Also Published As

Publication number Publication date
DE69220398D1 (de) 1997-07-24
EP0504758B1 (de) 1997-06-18
KR920018858A (ko) 1992-10-22
JPH04290430A (ja) 1992-10-15
JP2920848B2 (ja) 1999-07-19
EP0504758A3 (en) 1993-06-09
KR0175073B1 (ko) 1999-04-01
TW201847B (de) 1993-03-11
EP0504758A2 (de) 1992-09-23

Similar Documents

Publication Publication Date Title
DE69331817D1 (de) Herstellungsverfahren eines Halbleitersubstrat
GB2193346B (en) A method of rinsing a substrate from which the resist layer has been removed
DE69219268T2 (de) Planarisierung eines Halbleitersubstrates
ATA77695A (de) Bildung einer silberbeschichtung auf einem glasartigen substrat
GB2268329B (en) Methods of forming an interconnect on a semiconductor substrate
GB2241607B (en) Method of planarizing a dielectric formed over a semiconductor substrate
DE69216752D1 (de) Verfahren zur Herstellung einer Halbleiter-Scheibe
KR890008951A (ko) 실리콘 카바이드 기판의 제조방법
EP0057258A3 (en) Process of manufacturing polysilicon structures having 1 micron dimensions on silicon substrates comprising integrated circuits using plasma etching
DE69030129T2 (de) Herstellungsverfahren einer integrierten Halbleiterschaltung
EP0556795A3 (en) Method of manufacturing substrate having semiconductor on insulator
EP0502471A3 (en) Intrinsic gettering of a silicon substrate
DE69322058D1 (de) Plasma-Ätzverfahren
DE69333843D1 (de) Ätzverfahren für Silizium-Substrat
EP0607808A3 (de) Verfahren zur Ätzung eines halbleitender Substrats.
DE69205204T2 (de) Nassätzverfahren bei rotierenden Halbleitersubstraten.
DE69220398T2 (de) Plasma-Ätzverfahren einer Silizium enthaltenden Schicht
NO943139L (no) Plasmareaktor for en avsetnings- eller etsingsprosess
DE69203356T2 (de) Arbeitsfläche geringer Verunreinigung zur Herstellung von Silicium der Halbleitergeräte.
EP0600664A3 (de) Trocken-Ätz-Verfahren für eine Silizium-Dünnschicht.
FI943184A0 (fi) Plasmareaktori pinnoitus- tai etsausprosessia varten
EP0488230A3 (en) Method of manufacturing a semiconductor substrate having a dielectric isolation structure
GB9217349D0 (en) Method of etching a surface of a semiconductor
GB9110288D0 (en) Plasma deposition and etching of semiconductor substrates
DE69325910D1 (de) Feine Bearbeitung einer gekrümmten Halbleiterscheibe

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee