DE69219235T2 - Testen von Eingangs- und Ausgangsstufen in integrierten Schaltungen - Google Patents

Testen von Eingangs- und Ausgangsstufen in integrierten Schaltungen

Info

Publication number
DE69219235T2
DE69219235T2 DE69219235T DE69219235T DE69219235T2 DE 69219235 T2 DE69219235 T2 DE 69219235T2 DE 69219235 T DE69219235 T DE 69219235T DE 69219235 T DE69219235 T DE 69219235T DE 69219235 T2 DE69219235 T2 DE 69219235T2
Authority
DE
Germany
Prior art keywords
integrated circuits
output stages
testing input
testing
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69219235T
Other languages
English (en)
Other versions
DE69219235D1 (de
Inventor
Thomas B Pritchard
Casey D Hoekstra
Richard I Klaus
Douglas L Franz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69219235D1 publication Critical patent/DE69219235D1/de
Application granted granted Critical
Publication of DE69219235T2 publication Critical patent/DE69219235T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE69219235T 1991-07-02 1992-06-30 Testen von Eingangs- und Ausgangsstufen in integrierten Schaltungen Expired - Fee Related DE69219235T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/724,645 US5369645A (en) 1991-07-02 1991-07-02 Testing integrated circuit pad input and output structures

Publications (2)

Publication Number Publication Date
DE69219235D1 DE69219235D1 (de) 1997-05-28
DE69219235T2 true DE69219235T2 (de) 1997-08-07

Family

ID=24911260

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69219235T Expired - Fee Related DE69219235T2 (de) 1991-07-02 1992-06-30 Testen von Eingangs- und Ausgangsstufen in integrierten Schaltungen

Country Status (4)

Country Link
US (1) US5369645A (de)
EP (1) EP0525990B1 (de)
JP (1) JP3183563B2 (de)
DE (1) DE69219235T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2654352B2 (ja) * 1994-07-29 1997-09-17 日本電気アイシーマイコンシステム株式会社 半導体集積回路
US5796922A (en) * 1996-03-29 1998-08-18 Weber State University Trainable, state-sampled, network controller
US6079040A (en) * 1996-09-09 2000-06-20 Chips & Technologies, Inc. Module level scan testing
DE60021129T2 (de) * 1999-02-02 2006-05-18 Fujitsu Ltd., Kawasaki Verfahren und Vorrichtung zur Prüfung einer elektronischen Vorrichtung
DE60118089T2 (de) * 2000-03-02 2006-10-05 Texas Instruments Incorporated, Dallas Abtastschnittstelle mit Zeitmultiplexmerkmal zur Signalüberlagerung
US7382170B2 (en) * 2006-04-18 2008-06-03 Agere Systems Inc. Programmable delay circuit having reduced insertion delay
US7656657B2 (en) * 2006-05-30 2010-02-02 Hewlett-Packard Development Company, L.P. System and method for tool-less mounting of a device with a chassis
US8649180B2 (en) * 2006-05-30 2014-02-11 Hewlett-Packard Development Company, L.P. System and method for tool-less mounting of a bezel with an electronic device
US10664565B2 (en) 2017-05-19 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and system of expanding set of standard cells which comprise a library
KR102298923B1 (ko) 2017-05-24 2021-09-08 에스케이하이닉스 주식회사 반도체 장치, 테스트 방법 및 이를 포함하는 시스템

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485472A (en) * 1982-04-30 1984-11-27 Carnegie-Mellon University Testable interface circuit
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
JPH081760B2 (ja) * 1987-11-17 1996-01-10 三菱電機株式会社 半導体記憶装置
JPH01259274A (ja) * 1988-04-08 1989-10-16 Fujitsu Ltd 集積回路の試験方式
JPH02290573A (ja) * 1989-04-27 1990-11-30 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5003204A (en) * 1989-12-19 1991-03-26 Bull Hn Information Systems Inc. Edge triggered D-type flip-flop scan latch cell with recirculation capability
US5155733A (en) * 1990-12-26 1992-10-13 Ag Communication Systems Corporation Arrangement for testing digital circuit devices having bidirectional outputs

Also Published As

Publication number Publication date
JPH07174820A (ja) 1995-07-14
EP0525990B1 (de) 1997-04-23
DE69219235D1 (de) 1997-05-28
EP0525990A1 (de) 1993-02-03
US5369645A (en) 1994-11-29
JP3183563B2 (ja) 2001-07-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee