DE69131956T2 - Verarbeitungsprozessor zur Verbindung von Befehlen für einen Cache-Speicher - Google Patents

Verarbeitungsprozessor zur Verbindung von Befehlen für einen Cache-Speicher

Info

Publication number
DE69131956T2
DE69131956T2 DE69131956T DE69131956T DE69131956T2 DE 69131956 T2 DE69131956 T2 DE 69131956T2 DE 69131956 T DE69131956 T DE 69131956T DE 69131956 T DE69131956 T DE 69131956T DE 69131956 T2 DE69131956 T2 DE 69131956T2
Authority
DE
Germany
Prior art keywords
instructions
instruction
storage unit
computer system
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131956T
Other languages
English (en)
Other versions
DE69131956D1 (de
Inventor
Stamatis Vassiliadis
Bartholomew Blaner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69131956D1 publication Critical patent/DE69131956D1/de
Publication of DE69131956T2 publication Critical patent/DE69131956T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
DE69131956T 1991-01-15 1991-04-03 Verarbeitungsprozessor zur Verbindung von Befehlen für einen Cache-Speicher Expired - Fee Related DE69131956T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/642,011 US5295249A (en) 1990-05-04 1991-01-15 Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel

Publications (2)

Publication Number Publication Date
DE69131956D1 DE69131956D1 (de) 2000-03-09
DE69131956T2 true DE69131956T2 (de) 2000-07-20

Family

ID=24574797

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131956T Expired - Fee Related DE69131956T2 (de) 1991-01-15 1991-04-03 Verarbeitungsprozessor zur Verbindung von Befehlen für einen Cache-Speicher

Country Status (6)

Country Link
US (3) US5295249A (de)
EP (1) EP0496928B1 (de)
AT (1) ATE189540T1 (de)
BR (1) BR9101791A (de)
DE (1) DE69131956T2 (de)
ES (1) ES2142304T3 (de)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04143819A (ja) * 1989-12-15 1992-05-18 Hitachi Ltd 消費電力制御方法、半導体集積回路装置およびマイクロプロセツサ
JP2532300B2 (ja) * 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
EP0498067A2 (de) * 1991-02-08 1992-08-12 International Business Machines Corporation Mikrokodeerzeugung für eine Maschine mit skalierbarem Verbundbefehlssatz
DE69231011T2 (de) * 1991-02-08 2000-09-28 Fujitsu Ltd Cachespeicher zur Verarbeitung von Befehlsdaten und Datenprozessor mit demselben
JP2642529B2 (ja) * 1991-04-30 1997-08-20 株式会社東芝 並列プロセッサーの命令分配処理装置
US5860010A (en) * 1992-03-12 1999-01-12 Bull S.A. Use of language with similar representation for programs and data in distributed data processing
US5590348A (en) * 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
WO1994007197A1 (de) * 1992-09-22 1994-03-31 Siemens Aktiengesellschaft Verfahren zur bearbeitung eines anwenderprogramms auf einem parallelrechnersystem
JP2549256B2 (ja) * 1992-12-01 1996-10-30 インターナショナル・ビジネス・マシーンズ・コーポレイション 浮動小数点プロセッサへデータを転送する方法及び装置
JP3182591B2 (ja) * 1993-01-20 2001-07-03 株式会社日立製作所 マイクロプロセッサ
US6154828A (en) * 1993-06-03 2000-11-28 Compaq Computer Corporation Method and apparatus for employing a cycle bit parallel executing instructions
US5560034A (en) * 1993-07-06 1996-09-24 Intel Corporation Shared command list
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
US5434987A (en) * 1993-09-21 1995-07-18 Intel Corporation Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store
US5721854A (en) * 1993-11-02 1998-02-24 International Business Machines Corporation Method and apparatus for dynamic conversion of computer instructions
US6360313B1 (en) 1993-11-05 2002-03-19 Intergraph Corporation Instruction cache associative crossbar switch
DE69428004T2 (de) * 1993-11-05 2002-04-25 Intergraph Corp Superskalare Rechnerarchitektur mit Softwarescheduling
EP0974894B1 (de) * 1993-11-05 2002-02-27 Intergraph Corporation Befehlscachespeicher mit assoziativem Kreuzschienenschalter
US5509129A (en) * 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
JP3547482B2 (ja) * 1994-04-15 2004-07-28 株式会社日立製作所 情報処理装置
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
FR2731094B1 (fr) * 1995-02-23 1997-04-30 Dufal Frederic Procede et dispositif de commande simultanee des etats de controle des unites d'execution d'un processeur programmable
US5991869A (en) * 1995-04-12 1999-11-23 Advanced Micro Devices, Inc. Superscalar microprocessor including a high speed instruction alignment unit
EP0829045B1 (de) * 1995-06-01 2002-09-04 Fujitsu Limited Koordination von befehlsausgabe in einem parallelen befehlsverarbeitungssystem
US5850567A (en) * 1996-03-15 1998-12-15 Adaptec, Inc. Method for specifying concurrent execution of a string of I/O command blocks in a chain structure
WO1997036227A2 (en) * 1996-03-28 1997-10-02 Philips Electronics N.V. Method and computer system for processing a set of data elements on a sequential processor
US5867681A (en) * 1996-05-23 1999-02-02 Lsi Logic Corporation Microprocessor having register dependent immediate decompression
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US5958042A (en) * 1996-06-11 1999-09-28 Sun Microsystems, Inc. Grouping logic circuit in a pipelined superscalar processor
US5924128A (en) * 1996-06-20 1999-07-13 International Business Machines Corporation Pseudo zero cycle address generator and fast memory access
US6108655A (en) * 1996-07-19 2000-08-22 Cisco Technology, Inc. Method and apparatus for transmitting images and other objects over a computer network system
US5963723A (en) * 1997-03-26 1999-10-05 International Business Machines Corporation System for pairing dependent instructions having non-contiguous addresses during dispatch
US6012138A (en) * 1997-12-19 2000-01-04 Lsi Logic Corporation Dynamically variable length CPU pipeline for efficiently executing two instruction sets
US6014513A (en) * 1997-12-23 2000-01-11 University Of Washington Discovering code and data in a binary executable program
US6314493B1 (en) 1998-02-03 2001-11-06 International Business Machines Corporation Branch history cache
EP1457876B1 (de) * 1998-03-18 2017-10-04 Qualcomm Incorporated Systeme und Verfahren zur Steuerung eines digitalen Signalprozessors mit Befehlen von variabler Länge, Verfahren zur Generierung und Speicherung von diesen Befehlen und Speicher zur Speicherung diesen Befehlen
US6157998A (en) 1998-04-03 2000-12-05 Motorola Inc. Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers
US6237086B1 (en) * 1998-04-22 2001-05-22 Sun Microsystems, Inc. 1 Method to prevent pipeline stalls in superscalar stack based computing systems
US6230260B1 (en) 1998-09-01 2001-05-08 International Business Machines Corporation Circuit arrangement and method of speculative instruction execution utilizing instruction history caching
US6460116B1 (en) * 1998-09-21 2002-10-01 Advanced Micro Devices, Inc. Using separate caches for variable and generated fixed-length instructions
US6442672B1 (en) * 1998-09-30 2002-08-27 Conexant Systems, Inc. Method for dynamic allocation and efficient sharing of functional unit datapaths
US6957327B1 (en) * 1998-12-31 2005-10-18 Stmicroelectronics, Inc. Block-based branch target buffer
US6393551B1 (en) * 1999-05-26 2002-05-21 Infineon Technologies North America Corp. Reducing instruction transactions in a microprocessor
US6351802B1 (en) * 1999-12-03 2002-02-26 Intel Corporation Method and apparatus for constructing a pre-scheduled instruction cache
US6496193B1 (en) * 1999-12-30 2002-12-17 Intel Corporation Method and apparatus for fast loading of texture data into a tiled memory
JP3753584B2 (ja) * 2000-02-15 2006-03-08 富士通株式会社 画像処理装置
US6810031B1 (en) 2000-02-29 2004-10-26 Celox Networks, Inc. Method and device for distributing bandwidth
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
GB0022949D0 (en) * 2000-09-19 2000-11-01 Sgs Thomson Microelectronics Processing instruction words
US7143268B2 (en) * 2000-12-29 2006-11-28 Stmicroelectronics, Inc. Circuit and method for instruction compression and dispersal in wide-issue processors
US6889318B1 (en) * 2001-08-07 2005-05-03 Lsi Logic Corporation Instruction fusion for digital signal processor
JP3564445B2 (ja) * 2001-09-20 2004-09-08 松下電器産業株式会社 プロセッサ、コンパイル装置及びコンパイル方法
US7020765B2 (en) * 2002-09-27 2006-03-28 Lsi Logic Corporation Marking queue for simultaneous execution of instructions in code block specified by conditional execution instruction
US7590824B2 (en) * 2005-03-29 2009-09-15 Qualcomm Incorporated Mixed superscalar and VLIW instruction issuing and processing method and system
TW200910195A (en) * 2007-08-20 2009-03-01 Sunplus Technology Co Ltd A device of using serial bits to determine instruction length at a multi-mode processor and the method thereof
US20130061213A1 (en) * 2011-08-26 2013-03-07 Cognitive Electronics, Inc. Methods and systems for optimizing execution of a program in a parallel processing environment
US8405419B1 (en) * 2011-09-15 2013-03-26 International Business Machines Corporation Digital test system and method for value based data
DE102012216897B4 (de) * 2012-09-20 2014-09-11 Siemens Aktiengesellschaft Methoden zur Minimierung eines Truncation- Fehlers bei einem MRT
US9558000B2 (en) * 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts
US9766895B2 (en) * 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Opportunity multithreading in a multithreaded processor with instruction chaining capability
US10157164B2 (en) * 2016-09-20 2018-12-18 Qualcomm Incorporated Hierarchical synthesis of computer machine instructions
CN109656479B (zh) * 2018-12-11 2022-03-25 湖南国科微电子股份有限公司 一种构建存储器命令序列的方法及装置
US10956167B2 (en) * 2019-06-06 2021-03-23 International Business Machines Corporation Mechanism for instruction fusion using tags

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
JPS6028015B2 (ja) * 1980-08-28 1985-07-02 日本電気株式会社 情報処理装置
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
US4439828A (en) * 1981-07-27 1984-03-27 International Business Machines Corp. Instruction substitution mechanism in an instruction handling unit of a data processing system
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
EP0239081B1 (de) * 1986-03-26 1995-09-06 Hitachi, Ltd. Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen
JPH0810430B2 (ja) * 1986-11-28 1996-01-31 株式会社日立製作所 情報処理装置
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
US5075844A (en) * 1989-05-24 1991-12-24 Tandem Computers Incorporated Paired instruction processor precise exception handling mechanism
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
EP0459232B1 (de) * 1990-05-29 1998-12-09 National Semiconductor Corporation Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür

Also Published As

Publication number Publication date
EP0496928A2 (de) 1992-08-05
US5465377A (en) 1995-11-07
EP0496928B1 (de) 2000-02-02
ES2142304T3 (es) 2000-04-16
US5295249A (en) 1994-03-15
BR9101791A (pt) 1992-04-28
US6029240A (en) 2000-02-22
EP0496928A3 (en) 1993-01-27
ATE189540T1 (de) 2000-02-15
DE69131956D1 (de) 2000-03-09

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Legal Events

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8339 Ceased/non-payment of the annual fee