JPS5783846A - Operation system for variable length data - Google Patents

Operation system for variable length data

Info

Publication number
JPS5783846A
JPS5783846A JP15932180A JP15932180A JPS5783846A JP S5783846 A JPS5783846 A JP S5783846A JP 15932180 A JP15932180 A JP 15932180A JP 15932180 A JP15932180 A JP 15932180A JP S5783846 A JPS5783846 A JP S5783846A
Authority
JP
Japan
Prior art keywords
byte
length
mark
bytes
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15932180A
Other languages
Japanese (ja)
Other versions
JPS607813B2 (en
Inventor
Eizo Fujisaki
Kiyoshi Kawanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15932180A priority Critical patent/JPS607813B2/en
Publication of JPS5783846A publication Critical patent/JPS5783846A/en
Publication of JPS607813B2 publication Critical patent/JPS607813B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes

Abstract

PURPOSE:To make the operation processing of variable length data high-speed, by designating a byte mark to perform the operation processing of data, which is shorter than the access byte length, with the access byte length and by storing all bytes. CONSTITUTION:In case of the execution of this system, an operation circuit ALU of a processing byte length of plural bytes, a byte mark generating circuit BMG which generates a byte mark BM on a basis of the relation between an operand length L or L1 and L2 of the instruction word and the processing byte length, and a status circuit STG which generates status information on a basis of the byte mark BM and status information ST of the byte unit of the operation circuit ALU are provided. Data of the access byte length is read out from a storage device and is operated in the byte unit designated by the byte mark BM, and bytes which are not indicated by the byte mark are outputted as they are, and therefore, data of the access address length of the storage device is outputted from the operation circuit ALU. Consequently, all bytes are stored even for one-byte operation.
JP15932180A 1980-11-12 1980-11-12 Variable length calculation method Expired JPS607813B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15932180A JPS607813B2 (en) 1980-11-12 1980-11-12 Variable length calculation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15932180A JPS607813B2 (en) 1980-11-12 1980-11-12 Variable length calculation method

Publications (2)

Publication Number Publication Date
JPS5783846A true JPS5783846A (en) 1982-05-25
JPS607813B2 JPS607813B2 (en) 1985-02-27

Family

ID=15691241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15932180A Expired JPS607813B2 (en) 1980-11-12 1980-11-12 Variable length calculation method

Country Status (1)

Country Link
JP (1) JPS607813B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148478A2 (en) * 1983-12-23 1985-07-17 Hitachi, Ltd. A data processor with control of the significant bit lenghts of general purpose registers
JPS6454149U (en) * 1987-09-25 1989-04-04
EP0334131A2 (en) * 1988-03-10 1989-09-27 Nec Corporation Data processor performing operation on data having length shorter than one-word length

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148478A2 (en) * 1983-12-23 1985-07-17 Hitachi, Ltd. A data processor with control of the significant bit lenghts of general purpose registers
JPS6454149U (en) * 1987-09-25 1989-04-04
JPH0512821Y2 (en) * 1987-09-25 1993-04-05
EP0334131A2 (en) * 1988-03-10 1989-09-27 Nec Corporation Data processor performing operation on data having length shorter than one-word length

Also Published As

Publication number Publication date
JPS607813B2 (en) 1985-02-27

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