JPS607813B2 - Variable length calculation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable length calculation method for efficiently calculating variable length data.

When an arithmetic unit with a processing byte width of multiple bytes executes an instruction to retrieve data of a byte width shorter than the processing byte width from a storage device, perform an operation, and write the result to the storage device, conventionally, the storage device 0 to the data discussed from
was added to match the processing byte width of the arithmetic unit, the status information of the arithmetic result was also checked based on the processing byte width, and writing to the storage device was performed by read/modified write.

Such a modified write is necessary to create an error correction code (ECC) in the access byte width of the storage device, and is slower than a full byte store. The purpose of the present invention is to perform arithmetic processing on data that is less than the access byte width by specifying it with a byte mark without adding 0 to the access byte width, and to speed up the processing by making it possible to store all bytes. It is something to do.

Examples will be described in detail below. FIG. 1 is a block diagram of an embodiment of the present invention, where AI and A2 indicate the instruction format, OP is the instruction code, L1 and L2 are the first and second operand lengths, and B1 and DI are the first operand addresses. , B
2, D2 is the second operand address, which is the operand length when the first operand length and the second operand length are equal.

LR is a register for setting the operand length L1, L2 or L, ALUa is an arithmetic circuit for calculating the contents of register LR by the processing byte width for each calculation process, and BMQ is a byte mark BM according to the contents of register LR. The generated byte mark generation circuit, the AL mountain, and the first operand data O
STG is a status circuit, and CCG is a condition code generation circuit. A case will be described below in which the processing byte width of the arithmetic circuit ALU is 4 bytes, but the processing byte width in the present invention is not limited to this. Byte mark generation circuit BMG When the contents of register LR indicate 4 bytes or more, byte mark BM (BM
O to BM3) are all output as "1", and when indicating 3 bytes or less, the byte mark BM is output as "1" for the byte to be calculated.

The arithmetic circuit ALU performs arithmetic processing on a byte basis according to the byte mark BM, and generates status information ST on a byte basis.
is added to the status circuit STG. Also status circuit S
The TG uses the status information ST from the arithmetic circuit ALU and the byte mark BM from the byte mark generation circuit BMG to create status information such as zero, carry, overflow, negative, etc. of the operation result, and adds it to the condition code generation circuit CCG. Condition code CC is output and notified to the program, etc. Also, the arithmetic circuit AL
Since the operation result AR of U is 4-byte data, all bytes can be stored. FIG. 2 is a schematic explanatory diagram of the operation, in which the access byte width of the storage device MS is 4 bytes, and a
, b'c'd, when calculating data d in 4 bytes of data, conventionally, as shown in RDI, 1 byte of data d to be calculated is read out, the other 3 bytes are set to 0, and 4 bytes are data is applied to the arithmetic circuit ALU as the first operand data OPRI.

On the other hand, in the present invention, as shown in RD2, 4 bytes of data a, b, c, d are read out and applied to the arithmetic circuit ALU. At this time, since the operand length is specified as 1 byte, the byte mark BM has contents indicating an operation for 1 byte. Also, the second operand data?
In the case indicated by PR2, conventionally, the result of operation between the read data indicated by RDI and the second operand data OPR2 is indicated by ARI, and 3 bytes of data other than 1 byte of operation result data R become 0.

Therefore, when storing the operation result ARI in the storage device MS, writing must be performed by read-modify-write. On the other hand, in the present invention, the read data indicated by RD2 and the second operand data O
The result of the operation with PR2 is AR because the byte mark BM instructs the operation on the 4th byte data d.
2, and these 4 bytes of data a, b, c
, d can be stored as they are in the storage device MS. FIG. 3 is a block diagram of the arithmetic circuit portion of the embodiment of the present invention, where AR and BR are registers for setting the first and second operand data PR1 and OPR2;
ALUO to ALU3 are byte unit arithmetic circuits, RR is a register to set the arithmetic results, ... VI to mV4 are inverters, GI to G8, GI3 to GI5 are AND gates, G
9-GI2 is an or gate. Byte Mark BMO~
BM3 is all “1” when the operand length is 4 bytes or more.
'', and the AND gates G2, G4, G6, and G8 are opened, so the operation results of each operation circuit ALUO to ALU3 are set in the register RR.

Also, when the operand length L is 3 or less or the contents of the register LR are updated by arithmetic processing and become 3 or less, indicating 1, for example, byte marks BMO to BM2 become "0", byte mark BM3 becomes "1", and the storage device Even if 4 bytes of data are read from MS and set in register AR, bytes 0 to 2 are related to AND gates GI, G3, and G5, so they are set in register RR as they are, and only byte 3 is stored in the arithmetic circuit. It is calculated in ALU3 and sent to register R via AND gate G8 and OR gate GI2.
Set to R. That is, the contents of register RR are the same as those described with reference to FIG. Also, the arithmetic circuit ALUO
AND gates GI3 to GI5 and OR gates GI6 to GI8 are connected between ALU3 and byte mark B.
Corresponding to MI-BM3, signals GBI-GB3 for carry lookup (carry prediction) are connected as GI-G3, and signals PBI-PB3 are connected as P1-P3 to arithmetic circuits ALUO-2 at upper byte positions. Ru.

Based on the connected signals PI to P3 and GI to G3, carry inputs (carry signals) of the arithmetic circuits ALUO to ALU2 are created using the following logic. ALUO: P1, P2, P3
・Cin+P1・P2・G30 Pl. G20 GIALU
I:P2・P3・C:n+P2・G3＋G2ALU2:
P3.Cin+G3 Cin is a carry input (carry signal) for all ALUO to ALU3.

FIG. 4 is a block diagram of an example of the status circuit STG, with gates G20 to G27 and flip-flop FFI.
This outputs carry, overflow, and negative status information CON, and outputs zero status information Z from gates G28 to G32 and flip-flop FF2, and outputs zero status information Z from byte marks BMO to BM3 and byte unit arithmetic circuits ALUO to ALU3. This is obtained by logic with the status information BOS to B3S.

For example, when byte marks BMO to BM3 are "1" and calculation is performed on all 4 bytes, the flip-flop FFI is operated only by the status information BOS of byte 0, and the status information BOS to B3S of bytes 0 to 3 are all 0. Flip-flop FF2 is set and status information Z of zero is output only when this is indicated. Also, bite marks BMO to BM2 are “0” and bite mark BM3 is “1”.
``In other words, when performing an operation on one byte, flip-flop FFI is operated only by status information B3S of byte 3, and flip-flop FF2 is set only when status information B3S indicates 0.''
The condition code generation circuit CCG generates a condition code according to the output of the status circuit STG. output the option code.

Figure 5 shows status length and byte mark BM
, status information, etc., and the x mark in the zero check and carry output indicates the byte unit arithmetic circuit ALUO to ALU corresponding to that bit position.
This indicates that there is no need to consider status 3.

As explained above, the present invention has an arithmetic circuit ALU (ALUO to ALU3) with a processing byte width of multiple bytes, and a byte mark BM ( A bite mark generation circuit BMG that generates BMO to BM3) and a bite mark BM
(BMO to BM3) and arithmetic circuit ALU (ALUO to AL
Status information ST (BOS~B) in bytes of U3)
3S) and a status circuit STG for creating status information CON, Z of the calculation results, and a storage circuit MS.
The processing byte width data of the arithmetic circuit, that is, the access byte width data is extracted from byte mark BM (B
The calculation is performed in units of bytes specified by MO to BM3), and the bytes not specified by the byte mark are output as they are.
Since data with an access address width of 2 is output, all bytes can be stored even in a 1-byte operation, making it possible to speed up variable-length data arithmetic processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic operational explanatory diagram in comparison with a conventional example, FIG. 3 is a block diagram of an arithmetic circuit portion of an embodiment of the present invention, and FIG. FIG. 5 is a block diagram of the main part of the status circuit according to the embodiment of the present invention, and is an explanatory diagram of signs, bite marks, and status information. ALU, ALUO to ALU3 are arithmetic circuits, BMG is a byte mark generation circuit, STG is a status circuit, LR, A
R, BR, and RR are registers, and CCG is a condition code generation circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. An arithmetic circuit with a processing byte width of multiple bytes, a byte mark generation circuit that generates a byte mark based on the relationship between the operand length and the processing byte width, and a byte mark from the byte mark generation circuit and a byte from the arithmetic circuit. and a status circuit that creates status information of the operation result based on the status information of the unit, and performs the operation in the byte unit indicated by the byte mark on the operand data of the processing byte width of the arithmetic circuit, and performs the operation in the byte unit indicated by the byte mark. A variable length arithmetic method that is characterized by outputting bytes that are not processed as is.