JP3140812B2 - Five-operand shift instruction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a five-operand shift instruction system.

[0002]

2. Description of the Related Art Conventionally, shifting of double word data in an electronic computer required at least four instructions as shown in FIG. That is, the data a11 and a12 stored in the source registers rs1 and rs2, and b11,
b12 is shifted to the right by n bits and stored in the destination registers rd1 and rd2, first, as shown in FIG.
Of the data a11 and a12 stored in s1, the source register rs1 is shifted left (32-n) bits and stored in the register rt in order to leave the data a12.

Further, for the purpose of leaving the stored data a11 of the source register rs1, the source register rs1 is shifted right by n bits as shown in FIG.
The data is stored in the destination register rd1.

Further, as shown in FIG. 1D, data b11 and b12 stored in a source register rs2 are stored.
Is shifted to the right by n bits and stored in the destination register rd2, thereby storing the data b11 in a right-justified state.

Subsequently, as shown in FIG. 1E, the OR of the register rt and the destination register rd2 is ORed, and the result is stored in the destination register rd2 again.

[0006] By the above processing, as shown in FIG. 6 (a), it is possible to perform the n-bit shift processing to the right twice language data stored in the source register rs1, rs2.

As shown in FIG. 7A, the procedure for rotating the double word data a11 and a12 stored in the source register rs is as follows. The data of the source register rs is shifted leftward (32-n) bits and stored in the register rt, and only the double word data a12 is left-justified.

Then, as shown in FIG. 1C, the data in the source register rs is shifted rightward by n bits and stored in the destination register rd, and the double word data a11 is shifted to the right.

[0009] Subsequently, as shown in FIG. 2 (d), taking the OR of register rt and destination register rd, more to store the result in the destination register rd, is doubled word data a11, a12 Left and right
An alternate rotation process can be performed.

Further, as shown in FIG. 8A, when performing a process of realizing bit string insertion by a conventional shift instruction, first, as shown in FIG. 8B, the source registers rs1 and (2) ^{m + 1} -1) and register r
t, the m-bit double word data a12
With the right alignment.

Then, as shown in FIG. 1C, the n-bit double word data b stored in the source register rs2 is shifted left by m bits and stored in the destination register rd.

Further, as shown in FIG. 1D, the OR of the register rt and the destination register rd is taken, and the result is stored in the destination register rd. Store it in the destination register.

Subsequently, as shown in FIG. 2E, the source register rs1 is shifted rightward by m bits to register rt1.
, The double word data a11 is stored in the register rt again in a right-justified state.

Subsequently, as shown in FIG. 1F, the data in the register rt is shifted to the left by (m + n) bits.
The data is stored again in the register rt, and a blank space for (n + m) bits is formed on the right side.

Next, as shown in FIG. 1G, an OR of the register rt and the destination register rd is finally obtained, and the result is stored again in the destination register rd. Data a1
A data string in which double word data b is inserted between 1 and a12 is obtained.

[0016]

However, in such a conventional double word data shift processing method in a computer, it takes four cycles for double word shift, three cycles for rotation processing, and six cycles for bit string insertion. And rt for rotation processing and bit string insertion processing.
However, one extra work register is required, and the processing speed is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem. By using a five-operand shift instruction, double word data can be shifted, rotated, and bit-string operated at high speed. It is another object of the present invention to provide a five-operand shift instruction system.

[0018]

According to the present invention, two basic length source registers, these two basic length destination registers, and a total of five indicating a shift amount are provided.
A five-operand shift instruction method for performing a shift process using two operands. (I) In the case of shifting certain double word data, two consecutive word registers in which the double word data are stored are stored as the two source registers. (II) by specifying a register and storing the shifted doubleword data in two consecutive registers as the two destination registers,
When rotating data of a certain basic length by a predetermined length, the same register in which the data of the basic length is stored is designated as the two source registers, and the data of the part which overflows due to shift in one of the destination registers is designated. (3) the data is rotated by embedding the data in the other destination register so that the data is buried in the area where the space is left due to the shift, and storing the data rotated by a predetermined length in the other destination. When inserting data of the third length stored in the second register between data of the first length and data of the second length stored in the register, (1) The first register is a source register, and the empty third register is a destination register. Designated as, by the length of the second data is shifted these registers, the second of said first register to overflow by the shift
And (2) designating the second register as a source register and the third register as a destination register,
Shift these registers by the length of the data in
The third data of the second register that overflows due to this shift is stored in the third register,
(3) The first register shifted by the second data is designated as a source register, and the third register storing the second and third data is designated as a destination register. The first register is shifted by the free data length according to the third embodiment, and a part of the first data that overflows due to this shift is stored in a free area of the third register to insert data. It is characterized by doing.

[0019]

In the five-operand shift instruction method of the present invention, when shifting double word data by an arbitrary bit n, double word data set in the source registers rs1 and rs2 is set to the shift bit n. , N
Bit shift to destination register rd
By simply storing the data in 1, rd2, a shift by an arbitrary bit n can be performed.

When rotating n-bit data and m-bit data stored in a certain register, the same register is designated as source registers rs1 and rs2, and m bits are designated as a shift amount. To the destination registers rd1, r
d2, the destination register r
Data resulting from rotation of the data stored in the source register rs1 can be extracted from d2.

Further, when inserting data of an n-bit string into double word data of the source register rs1 composed of m bits and (32-m) bits, the source register r
The data of s1 is shifted to the right by m bits and the register rt
And a destination register rd1 and an n-bit shift operation is performed on the source register rs2 storing the n-bit double word data for insertion and the destination register rd1 described above. In the third cycle, the data of the register rt and the data of the destination register rd1 are (32− (n +
m)) By shifting the bits and storing them again in rd1, new data with n-bit doubleword data inserted therein can be extracted from the destination register rd1.

Thus, any bit shift,
Rotation and bit string insertion can be performed at high speed with only a small number of shift operations.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an example of the configuration of a five-operand shift instruction system according to the present invention, which is configured in a 32 × 2-bit instruction word format, and has a 10-bit instruction code op1 and a 5-bit length instruction code op1. An instruction code op2, an instruction code op3 which is the second word of the 64-bit length instruction, destination registers rd1 and rd2 of 6-bit length, source registers rs1 and rs2 of 6-bit length, and a shift width designation code b1; It is composed of

The operation of shifting, rotating, and inserting an arbitrary bit string using the five-operand shift instruction method will be described below.

As shown in FIGS. 2 and 3, n is set to the shift code b1 and SRLL (Sift Right Log
ical Long) is performed with the shift code b1 = n, the double word data a1 and b1 stored in the source registers rs1 and rs2 are shifted right by n bits and stored in the destination registers rd1 and rd2. , Destination register rd1 stores the remaining portion shifted right by n bits of original double word data a1, and destination register rd2 shifts n bits right of original double word data b1 to the right. And the right n bits of the original double word data a1 are stored at the same time. As a result, the result of shifting right by n bits in only one cycle is obtained.

As shown in FIG. 3, SRAL (Sift
Right Arithmetic Long) operation is performed using shift code b =
m, the source registers rs1, rs
The double word data a1 and b1 stored in
In the destination registers rd1 and rd2,
It is shifted right by m bits, and 1 is set for the left m bits of the destination register rd1.

In the case where the rotation process is performed using the five-operand shift instruction of the above embodiment, the method shown in FIG. 4 is followed. That is, the source registers rs1, r
The same double word data a11 and a12 are stored in each of s2, and for these source registers rs1 and rs2,
SRL that shifts to the right by n bits of data a12
By performing the L operation, only the double word data a11 is stored in the destination register rd1, and the source register rs is stored in the destination register rd2.
Only the double word data a12 of 1 and the double word data a11 of the original source register rs2 are stored, and as a result, the rotated result is stored in the destination register rd2.

Next, a method of implementing the bit string insertion processing will be described.

FIG. 5 shows a method of implementing the bit string insertion process. As shown in FIG.
When the data a13 stored in the source register rs2 is inserted into the data a11 and a12 stored in the first register rs1, first, as shown in FIG. By performing SLLL (Shift Left Logical Long) operation for m bits and storing the result in the register rt and the destination register rd1, the double word data a11 is stored in the register rt right-justified, and the destination register rd1 is stored in the destination register rd1. The m-bit data a12 is stored left-justified .

In the subsequent second cycle, the source register r
s2 and the destination register rd1 are shifted by the bit length n of the data a13 and SLLL is performed.
And a12 are stored.

Subsequently, in the third cycle shown in FIG. 4D, the (32- (m + n)) shift operation and the SLLL are performed on the register rt and the destination register rd1, and finally the destination Data in which n-bit data a13 is inserted between the data a11 and a12 in the register rd1 can be obtained.

Thus, in the five-operand shift instruction system of this embodiment, the shift operation and the rotate operation of an arbitrary number of bits can be performed by only one cycle of shift operation, and the bit string insertion operation is as few as three cycles. This can be performed by a shift operation, and high-speed processing can be realized.

[0034]

As described above, according to the present invention, the result obtained by shifting two source registers by an arbitrary bit is represented by 2
Since it is a five-operand type shift instruction system in which data is stored in one destination register, an arbitrary shift or rotate can be completed in one cycle of shift processing simply by appropriately setting the number of shift bits.
Also, the bit string insertion processing can be executed in a small number of cycles, and a high-speed shift processing can be realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a command word format according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an SRLL operation in the embodiment.

FIG. 3 is an explanatory diagram showing an SRAL operation in the embodiment.

FIG. 4 is an explanatory view showing a rotation operation according to the embodiment.

FIG. 5 is an explanatory diagram showing a bit string insertion process according to the embodiment.

FIG. 6 is an explanatory diagram showing a shift operation in a conventional example.

FIG. 7 is an explanatory view showing a rotation operation of a conventional example.

FIG. 8 is an explanatory diagram showing a conventional bit string insertion process.

[Explanation of symbols]

 op1, op2, op3 instruction code rs1, rs2 source register rd1, rd2 destination register b shift code a1, a11, a12, a13 double word data b1, b11, b12 double word data rt register

Continued on the front page (56) References JP-A-58-184649 (JP, A) JP-A-62-143130 (JP, A) JP-A-2-130634 (JP, A) JP-A-59-180732 (JP, A) JP-A-3-189728 (JP, A) JP-A-57-27336 (JP, A) JP-A-59-62950 (JP, A) JP-A-59-79495 (JP, A) JP-A-57-50034 (JP, A) JP-A-57-76634 (JP, A) JP-A-3-55629 (JP, A) JP-A-62-85327 (JP, A) JP-A-64-81033 (JP, A) A) JP-A-5-88887 (JP, A) Yukio Kaneda, "Microprocessors and RISC", Ohmsha, May 25, 1991, pp. 94-132 (58) Fields investigated (Int. Cl ^7, DB name) G06F 9/30 -. 9/42 G06F 7/00

Claims (1)

(57) [Claims] 1. A five-operand shift instruction method for performing a shift process using two basic length source registers, a destination register having these two basic lengths, and a total of five operands indicating a shift amount. When shifting certain double word data, two consecutive registers storing the double word data are designated as the two source registers, and the shifted double word data is stored in the two destination registers. In the case where data of a certain basic length is rotated by a predetermined length, the same register storing the data of the basic length is designated as the two source registers, and one destination The data in the register that overflows due to the shift is The first destination data stored in the first register is shifted by a predetermined length in the other destination by shifting the data so as to be embedded in an area where the shift becomes empty in the destination register. When inserting the third length data stored in the second register between the first register and the second length data, (1) the first register is a source register and an empty third
Are designated as destination registers, these registers are shifted by the length of the second data, and the second data of the first register that overflows due to this shift is stored in the third register. (2) the second register is a source register, and the third register is
Are designated as destination registers, these registers are shifted by the length of the third data, and the third data of the second register that overflows due to this shift is stored in the third register. (3) specifying the first register shifted by the second data as a source register, and specifying the third register storing the second and third data as a destination register, Shifting the first register by an empty data length of the third register, and storing a part of the first data that overflows due to the shift in an empty area of the third register. 5 operand type shift instruction method.