CA2040637A1 - Compounding preprocessor for cache - Google Patents

Compounding preprocessor for cache

Info

Publication number
CA2040637A1
CA2040637A1 CA 2040637 CA2040637A CA2040637A1 CA 2040637 A1 CA2040637 A1 CA 2040637A1 CA 2040637 CA2040637 CA 2040637 CA 2040637 A CA2040637 A CA 2040637A CA 2040637 A1 CA2040637 A1 CA 2040637A1
Authority
CA
Canada
Prior art keywords
instructions
instruction
storage unit
computer system
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2040637
Other languages
French (fr)
Other versions
CA2040637C (en
Inventor
Bartholomew Blaner
Stamatis Vassiliadis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/642,011 external-priority patent/US5295249A/en
Application filed by Individual filed Critical Individual
Publication of CA2040637A1 publication Critical patent/CA2040637A1/en
Application granted granted Critical
Publication of CA2040637C publication Critical patent/CA2040637C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream.
These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit. At instruction issue time, the compounding information for the instructions is examined and those instructions indicated for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.
CA 2040637 1990-05-04 1991-04-17 Compounding preprocessor for cache Expired - Fee Related CA2040637C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US51938490A 1990-05-04 1990-05-04
US519,384 1990-05-04
US07/642,011 US5295249A (en) 1990-05-04 1991-01-15 Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
US642,011 1991-01-15

Publications (2)

Publication Number Publication Date
CA2040637A1 true CA2040637A1 (en) 1991-11-05
CA2040637C CA2040637C (en) 1998-02-10

Family

ID=27059822

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2040637 Expired - Fee Related CA2040637C (en) 1990-05-04 1991-04-17 Compounding preprocessor for cache

Country Status (1)

Country Link
CA (1) CA2040637C (en)

Also Published As

Publication number Publication date
CA2040637C (en) 1998-02-10

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