DE69131186T2 - Verfahren zum Steuern eines Pufferspeichers für einen Magnetplattenspeicher - Google Patents

Verfahren zum Steuern eines Pufferspeichers für einen Magnetplattenspeicher

Info

Publication number
DE69131186T2
DE69131186T2 DE69131186T DE69131186T DE69131186T2 DE 69131186 T2 DE69131186 T2 DE 69131186T2 DE 69131186 T DE69131186 T DE 69131186T DE 69131186 T DE69131186 T DE 69131186T DE 69131186 T2 DE69131186 T2 DE 69131186T2
Authority
DE
Germany
Prior art keywords
bit
address
error detection
buffer memory
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131186T
Other languages
German (de)
English (en)
Other versions
DE69131186D1 (de
Inventor
Dhiru N. Desai
David M. Lewis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Technology International
Seagate Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology International, Seagate Technology LLC filed Critical Seagate Technology International
Publication of DE69131186D1 publication Critical patent/DE69131186D1/de
Application granted granted Critical
Publication of DE69131186T2 publication Critical patent/DE69131186T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
  • Dram (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE69131186T 1990-03-02 1991-02-26 Verfahren zum Steuern eines Pufferspeichers für einen Magnetplattenspeicher Expired - Fee Related DE69131186T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/487,740 US5280601A (en) 1990-03-02 1990-03-02 Buffer memory control system for a magnetic disc controller

Publications (2)

Publication Number Publication Date
DE69131186D1 DE69131186D1 (de) 1999-06-10
DE69131186T2 true DE69131186T2 (de) 1999-08-26

Family

ID=23936929

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131186T Expired - Fee Related DE69131186T2 (de) 1990-03-02 1991-02-26 Verfahren zum Steuern eines Pufferspeichers für einen Magnetplattenspeicher

Country Status (5)

Country Link
US (1) US5280601A (cg-RX-API-DMAC7.html)
EP (1) EP0444885B1 (cg-RX-API-DMAC7.html)
JP (1) JP2772150B2 (cg-RX-API-DMAC7.html)
DE (1) DE69131186T2 (cg-RX-API-DMAC7.html)
SG (1) SG47724A1 (cg-RX-API-DMAC7.html)

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US5655147A (en) * 1991-02-28 1997-08-05 Adaptec, Inc. SCSI host adapter integrated circuit utilizing a sequencer circuit to control at least one non-data SCSI phase without use of any processor
IL100127A0 (en) * 1991-03-11 1992-08-18 Future Domain Corp Scsi controller
US5371861A (en) * 1992-09-15 1994-12-06 International Business Machines Corp. Personal computer with small computer system interface (SCSI) data flow storage controller capable of storing and processing multiple command descriptions ("threads")
US5537425A (en) * 1992-09-29 1996-07-16 International Business Machines Corporation Parity-based error detection in a memory controller
US5659690A (en) * 1992-10-15 1997-08-19 Adaptec, Inc. Programmably configurable host adapter integrated circuit including a RISC processor
US5379261A (en) * 1993-03-26 1995-01-03 United Memories, Inc. Method and circuit for improved timing and noise margin in a DRAM
KR0139776B1 (ko) * 1993-11-26 1998-07-15 이헌조 씨디 그래픽스 디코더의 디램제어장치
WO1995016950A1 (en) * 1993-12-14 1995-06-22 Apple Computer, Inc. Method and apparatus for transferring data between a computer and a peripheral storage device
US5983309A (en) * 1994-07-27 1999-11-09 Seagate Technology, Inc. Autonomous high speed address translation with defect management for hard disc drives
US5729719A (en) * 1994-09-07 1998-03-17 Adaptec, Inc. Synchronization circuit for clocked signals of similar frequencies
WO1996032674A2 (en) * 1995-04-13 1996-10-17 Cirrus Logic, Inc. Semiconductor memory device for mass storage block access applications
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US5765203A (en) * 1995-12-19 1998-06-09 Seagate Technology, Inc. Storage and addressing method for a buffer memory control system for accessing user and error imformation
US6021482A (en) * 1997-07-22 2000-02-01 Seagate Technology, Inc. Extended page mode with a skipped logical addressing for an embedded longitudinal redundancy check scheme
US6148388A (en) * 1997-07-22 2000-11-14 Seagate Technology, Inc. Extended page mode with memory address translation using a linear shift register
US6009547A (en) * 1997-12-03 1999-12-28 International Business Machines Corporation ECC in memory arrays having subsequent insertion of content
US6925589B1 (en) * 1998-10-29 2005-08-02 International Business Machines Corporation Method for translating physical cell-coordinates of a memory product to n-dimensional addresses
JP3778540B2 (ja) * 1999-05-17 2006-05-24 東芝デジタルメディアエンジニアリング株式会社 信号処理回路及び情報記録装置
JP2002170399A (ja) * 2000-12-05 2002-06-14 Fujitsu Ltd 半導体装置
US20040268033A1 (en) * 2003-06-24 2004-12-30 Seagate Technology Llc Refreshing data in a data storage device
US7836380B2 (en) * 2006-10-31 2010-11-16 Intel Corporation Destination indication to aid in posted write buffer loading
US7961532B2 (en) * 2008-06-27 2011-06-14 Rambus Inc. Bimodal memory controller

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2112256B (en) * 1981-11-18 1985-11-06 Texas Instruments Ltd Memory apparatus
US4514806A (en) * 1982-09-30 1985-04-30 Honeywell Information Systems Inc. High speed link controller wraparound test logic
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4916603A (en) * 1985-03-18 1990-04-10 Wang Labortatories, Inc. Distributed reference and change table for a virtual memory system
US4819152A (en) * 1985-04-05 1989-04-04 Raytheon Company Method and apparatus for addressing a memory by array transformations
US4672613A (en) * 1985-11-01 1987-06-09 Cipher Data Products, Inc. System for transferring digital data between a host device and a recording medium
JPS62149099A (ja) * 1985-12-23 1987-07-03 Toshiba Corp メモリアクセス制御回路
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4845664A (en) * 1986-09-15 1989-07-04 International Business Machines Corp. On-chip bit reordering structure
JPS63186345A (ja) * 1987-01-29 1988-08-01 Toshiba Corp アドレス多重化制御回路
US5007020A (en) * 1987-03-18 1991-04-09 Hayes Microcomputer Products, Inc. Method for memory addressing and control with reversal of higher and lower address
US5057837A (en) * 1987-04-20 1991-10-15 Digital Equipment Corporation Instruction storage method with a compressed format using a mask word
EP0303752B1 (en) * 1987-08-20 1993-06-02 International Business Machines Corporation Memory access control device in a mixed data format system
US4992956A (en) * 1987-10-08 1991-02-12 Advanced Micro Devices, Inc. Apparatus for assembling data for supply to a scanning output device
US4888773A (en) * 1988-06-15 1989-12-19 International Business Machines Corporation Smart memory card architecture and interface
US4916654A (en) * 1988-09-06 1990-04-10 International Business Machines Corporation Method for transfer of data via a window buffer from a bit-planar memory to a selected position in a target memory
US5058005A (en) * 1988-09-09 1991-10-15 Compaq Computer Corporation Computer system with high speed data transfer capabilities
US5065312A (en) * 1989-08-01 1991-11-12 Digital Equipment Corporation Method of converting unique data to system data

Also Published As

Publication number Publication date
JP2772150B2 (ja) 1998-07-02
JPH06131124A (ja) 1994-05-13
SG47724A1 (en) 1998-04-17
EP0444885B1 (en) 1999-05-06
US5280601A (en) 1994-01-18
DE69131186D1 (de) 1999-06-10
EP0444885A3 (cg-RX-API-DMAC7.html) 1995-01-25
HK1013344A1 (en) 1999-08-20
EP0444885A2 (en) 1991-09-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SEAGATE TECHNOLOGY LLC, SCOTTS VALLEY, CALIF., US

8328 Change in the person/name/address of the agent

Free format text: HENKEL, FEILER & HAENZEL, 81675 MUENCHEN

8339 Ceased/non-payment of the annual fee