DE69128021D1 - Lese-/Schreibe-Speicher mit einem verbesserten Schreibtreiber - Google Patents

Lese-/Schreibe-Speicher mit einem verbesserten Schreibtreiber

Info

Publication number
DE69128021D1
DE69128021D1 DE69128021T DE69128021T DE69128021D1 DE 69128021 D1 DE69128021 D1 DE 69128021D1 DE 69128021 T DE69128021 T DE 69128021T DE 69128021 T DE69128021 T DE 69128021T DE 69128021 D1 DE69128021 D1 DE 69128021D1
Authority
DE
Germany
Prior art keywords
write
read
improved
driver
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128021T
Other languages
English (en)
Other versions
DE69128021T2 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69128021D1 publication Critical patent/DE69128021D1/de
Application granted granted Critical
Publication of DE69128021T2 publication Critical patent/DE69128021T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69128021T 1990-12-13 1991-12-11 Lese-/Schreibe-Speicher mit einem verbesserten Schreibtreiber Expired - Fee Related DE69128021T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/627,059 US5267197A (en) 1990-12-13 1990-12-13 Read/write memory having an improved write driver

Publications (2)

Publication Number Publication Date
DE69128021D1 true DE69128021D1 (de) 1997-11-27
DE69128021T2 DE69128021T2 (de) 1998-03-12

Family

ID=24513017

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128021T Expired - Fee Related DE69128021T2 (de) 1990-12-13 1991-12-11 Lese-/Schreibe-Speicher mit einem verbesserten Schreibtreiber

Country Status (5)

Country Link
US (1) US5267197A (de)
EP (1) EP0490652B1 (de)
JP (1) JP3322412B2 (de)
KR (1) KR100228622B1 (de)
DE (1) DE69128021T2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0852381B1 (de) * 1992-11-12 2005-11-16 ProMOS Technologies, Inc. Leseverstärker mit lokalen Schreibtreibern
US5369610A (en) * 1993-11-26 1994-11-29 United Microelectronics Corporation Static memory with improved write-recovery
US6101618A (en) * 1993-12-22 2000-08-08 Stmicroelectronics, Inc. Method and device for acquiring redundancy information from a packaged memory chip
JP3181479B2 (ja) * 1994-12-15 2001-07-03 沖電気工業株式会社 半導体記憶装置
EP0724209A1 (de) * 1995-01-25 1996-07-31 International Business Machines Corporation Leistungssteuerungssystem für integrierte Schaltungen
KR0171954B1 (ko) * 1995-06-30 1999-03-30 김주용 데이타 버스 구동 회로
JPH09231770A (ja) * 1996-01-19 1997-09-05 Sgs Thomson Microelectron Inc メモリセルへの書込を終了させる回路及び方法
US5657292A (en) * 1996-01-19 1997-08-12 Sgs-Thomson Microelectronics, Inc. Write pass through circuit
US5801563A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Output driver circuitry having a single slew rate resistor
US5767709A (en) * 1996-01-19 1998-06-16 Sgs-Thomson Microelectronics, Inc. Synchronous test mode initalization
US5864696A (en) * 1996-01-19 1999-01-26 Stmicroelectronics, Inc. Circuit and method for setting the time duration of a write to a memory cell
JPH09282886A (ja) * 1996-01-19 1997-10-31 Sgs Thomson Microelectron Inc メモリセルへの書込の開始をトラッキングする回路及び方法
US5712584A (en) * 1996-01-19 1998-01-27 Sgs-Thomson Microelectronics, Inc. Synchronous stress test control
US5619456A (en) * 1996-01-19 1997-04-08 Sgs-Thomson Microelectronics, Inc. Synchronous output circuit
US5701275A (en) * 1996-01-19 1997-12-23 Sgs-Thomson Microelectronics, Inc. Pipelined chip enable control circuitry and methodology
US5661691A (en) * 1996-05-23 1997-08-26 Vanguard International Semiconductor Corporation Simple layout low power data line sense amplifier design
JPH1063581A (ja) * 1996-08-26 1998-03-06 Nec Corp メモリ書き込み制御回路
US5828239A (en) * 1997-04-14 1998-10-27 International Business Machines Corporation Sense amplifier circuit with minimized clock skew effect
JP3244048B2 (ja) * 1998-05-19 2002-01-07 日本電気株式会社 半導体記憶装置
KR100543200B1 (ko) * 1998-06-15 2006-04-12 주식회사 하이닉스반도체 스태틱램의 비트라인 클램핑회로
DE10032271C2 (de) * 2000-07-03 2002-08-01 Infineon Technologies Ag MRAM-Anordnung
US6552943B1 (en) * 2000-08-31 2003-04-22 United Memories, Inc. Sense amplifier for dynamic random access memory (“DRAM”) devices having enhanced read and write speed
US6549452B1 (en) 2001-12-20 2003-04-15 Integrated Device Technology, Inc. Variable width wordline pulses in a memory device
US6862208B2 (en) * 2003-04-11 2005-03-01 Freescale Semiconductor, Inc. Memory device with sense amplifier and self-timed latch
KR100533384B1 (ko) * 2004-04-12 2005-12-06 주식회사 하이닉스반도체 저진폭 전압구동 글로벌 입출력 라인을 갖는 반도체메모리 장치
KR100720260B1 (ko) 2004-11-15 2007-05-22 주식회사 하이닉스반도체 반도체 메모리 장치의 로컬 입출력 라인 프리차지 회로
US20060245240A1 (en) * 2005-04-28 2006-11-02 Ibm Corporation Method and apparatus for reducing time delay through static bitlines of a static memory
US7324368B2 (en) * 2006-03-30 2008-01-29 Arm Limited Integrated circuit memory with write assist
US20070230004A1 (en) * 2006-04-04 2007-10-04 Johnson Yen Read channel/hard disk controller interface including power-on reset circuit
KR100837801B1 (ko) * 2006-06-29 2008-06-16 주식회사 하이닉스반도체 반도체 메모리 장치
JP4504397B2 (ja) * 2007-05-29 2010-07-14 株式会社東芝 半導体記憶装置
US9013940B2 (en) * 2013-02-28 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Sense amplifier
US9281056B2 (en) 2014-06-18 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Static random access memory and method of using the same
US10755770B2 (en) * 2016-09-30 2020-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for writing to a bit cell
DE102017117791A1 (de) 2016-09-30 2018-04-05 Taiwan Semiconductor Manufacturing Co. Ltd. Schaltung und Verfahren zum Schreiben auf eine Bitzelle

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3778783A (en) * 1971-11-29 1973-12-11 Mostek Corp Dynamic random access memory
US3727196A (en) * 1971-11-29 1973-04-10 Mostek Corp Dynamic random access memory
JPS595989B2 (ja) * 1980-02-16 1984-02-08 富士通株式会社 スタティック型ランダムアクセスメモリ
US4570243A (en) * 1982-07-16 1986-02-11 Inmos Corporation Low power I/O scheme for semiconductor memories
US4575823A (en) * 1982-08-17 1986-03-11 Westinghouse Electric Corp. Electrically alterable non-volatile memory
JPS63144488A (ja) * 1986-12-06 1988-06-16 Fujitsu Ltd 半導体記憶装置
US4825413A (en) * 1987-02-24 1989-04-25 Texas Instruments Incorporated Bipolar-CMOS static ram memory device
US4862421A (en) * 1988-02-16 1989-08-29 Texas Instruments Incorporated Sensing and decoding scheme for a BiCMOS read/write memory
US4866674A (en) * 1988-02-16 1989-09-12 Texas Instruments Incorporated Bitline pull-up circuit for a BiCMOS read/write memory
US4939693A (en) * 1989-02-14 1990-07-03 Texas Instruments Incorporated BiCMOS static memory with improved performance stability

Also Published As

Publication number Publication date
JPH04291093A (ja) 1992-10-15
KR100228622B1 (ko) 1999-11-01
EP0490652A2 (de) 1992-06-17
EP0490652B1 (de) 1997-10-22
JP3322412B2 (ja) 2002-09-09
EP0490652A3 (en) 1993-01-27
US5267197A (en) 1993-11-30
DE69128021T2 (de) 1998-03-12
KR920013449A (ko) 1992-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee