DE69114900D1 - Schaltung zur Erzeugung eines Abtasttaktes. - Google Patents

Schaltung zur Erzeugung eines Abtasttaktes.

Info

Publication number
DE69114900D1
DE69114900D1 DE69114900T DE69114900T DE69114900D1 DE 69114900 D1 DE69114900 D1 DE 69114900D1 DE 69114900 T DE69114900 T DE 69114900T DE 69114900 T DE69114900 T DE 69114900T DE 69114900 D1 DE69114900 D1 DE 69114900D1
Authority
DE
Germany
Prior art keywords
generating
circuit
sampling clock
sampling
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114900T
Other languages
English (en)
Other versions
DE69114900T2 (de
Inventor
Kazuya Maeshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69114900D1 publication Critical patent/DE69114900D1/de
Publication of DE69114900T2 publication Critical patent/DE69114900T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/935—Regeneration of digital synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Synchronizing For Television (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Television Systems (AREA)
DE69114900T 1990-03-30 1991-02-14 Schaltung zur Erzeugung eines Abtasttaktes. Expired - Fee Related DE69114900T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2086274A JPH0834589B2 (ja) 1990-03-30 1990-03-30 サンプリングクロック発生回路

Publications (2)

Publication Number Publication Date
DE69114900D1 true DE69114900D1 (de) 1996-01-11
DE69114900T2 DE69114900T2 (de) 1996-04-11

Family

ID=13882247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114900T Expired - Fee Related DE69114900T2 (de) 1990-03-30 1991-02-14 Schaltung zur Erzeugung eines Abtasttaktes.

Country Status (4)

Country Link
US (1) US5168360A (de)
EP (1) EP0454955B1 (de)
JP (1) JPH0834589B2 (de)
DE (1) DE69114900T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2776098B2 (ja) * 1991-11-27 1998-07-16 松下電器産業株式会社 クロック再生回路および時間軸誤差補正装置
JPH05207326A (ja) * 1992-01-28 1993-08-13 Matsushita Electric Ind Co Ltd 水平圧縮ｐｌｌ回路
US5734877A (en) * 1992-09-09 1998-03-31 Silicon Graphics, Inc. Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns
JP3487119B2 (ja) * 1996-05-07 2004-01-13 松下電器産業株式会社 ドットクロック再生装置
JP2000232355A (ja) * 1999-02-09 2000-08-22 Mitsubishi Electric Corp 位相同期回路
EP1439536B1 (de) * 2003-01-20 2015-07-29 Media Tek Inc. Abtasttakterzeugung zur Dekodierung von BCA-Daten
GB2430089B (en) * 2005-09-08 2007-10-17 Motorola Inc RF synthesizer and RF transmitter or receiver incorporating the synthesizer
KR100790984B1 (ko) * 2006-03-03 2008-01-02 삼성전자주식회사 Ｄｏｔ 클럭 신호의 주파수에 관계없이 일정한 주파수의시스템 클럭 신호를 생성하는 디스플레이용 구동 집적회로및 시스템 클럭 신호 생성 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3824379A (en) * 1971-12-30 1974-07-16 Nippon Gakki Siezo Kk Variable frequency dividing circuit
EP0138164B1 (de) * 1983-10-14 1991-09-04 Hitachi, Ltd. Verfahren und Gerät für die Abtastung und Verarbeitung eines Videosignals
US4577225A (en) * 1984-08-31 1986-03-18 Rca Corporation Progressive scan video processor having common memories for video interpolation and speed-up
JPS61139174A (ja) * 1984-12-11 1986-06-26 Sony Corp 倍速変換装置
EP0392569A3 (de) * 1985-04-12 1990-11-28 Tektronix Inc. Digitale Einstellung der Phase
US4827341A (en) * 1986-12-16 1989-05-02 Fuji Photo Equipment Co., Ltd. Synchronizing signal generating circuit
US4779132A (en) * 1987-07-08 1988-10-18 Zenith Electronics Corporation Video monitor using encoded sync signals
US4757264A (en) * 1987-10-08 1988-07-12 American Telephone And Telegraph Company, At&T Bell Laboratories Sample clock signal generator circuit
DE68915228T2 (de) * 1988-09-02 1994-12-15 Sanyo Electric Co Phasensynchronisierschaltung in einem Videosignalempfänger und Verfahren zur Herstellung der Phasensynchronisation.
JPH071423B2 (ja) * 1988-12-20 1995-01-11 株式会社山下電子設計 パルス発生回路
DE3905669C2 (de) * 1989-02-24 1996-03-07 Broadcast Television Syst Schaltungsanordnung zur Ableitung von Synchronsignalen aus einem digitalen Videosignal

Also Published As

Publication number Publication date
US5168360A (en) 1992-12-01
DE69114900T2 (de) 1996-04-11
EP0454955B1 (de) 1995-11-29
JPH03284083A (ja) 1991-12-13
JPH0834589B2 (ja) 1996-03-29
EP0454955A1 (de) 1991-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee