DE69323341T2 - Schaltung zur Erzeugung eines ausgeglichenen Puls-Pausenverhältnisses - Google Patents

Schaltung zur Erzeugung eines ausgeglichenen Puls-Pausenverhältnisses

Info

Publication number
DE69323341T2
DE69323341T2 DE69323341T DE69323341T DE69323341T2 DE 69323341 T2 DE69323341 T2 DE 69323341T2 DE 69323341 T DE69323341 T DE 69323341T DE 69323341 T DE69323341 T DE 69323341T DE 69323341 T2 DE69323341 T2 DE 69323341T2
Authority
DE
Germany
Prior art keywords
generating
circuit
pause ratio
balanced pulse
balanced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69323341T
Other languages
English (en)
Other versions
DE69323341D1 (de
Inventor
Michael S Ehrlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quantum Corp
Original Assignee
Quantum Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quantum Corp filed Critical Quantum Corp
Publication of DE69323341D1 publication Critical patent/DE69323341D1/de
Application granted granted Critical
Publication of DE69323341T2 publication Critical patent/DE69323341T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
DE69323341T 1992-04-14 1993-04-05 Schaltung zur Erzeugung eines ausgeglichenen Puls-Pausenverhältnisses Expired - Fee Related DE69323341T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/868,984 US5227671A (en) 1992-04-14 1992-04-14 Circuit providing equalized duty cycle output

Publications (2)

Publication Number Publication Date
DE69323341D1 DE69323341D1 (de) 1999-03-18
DE69323341T2 true DE69323341T2 (de) 1999-06-10

Family

ID=25352710

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69323341T Expired - Fee Related DE69323341T2 (de) 1992-04-14 1993-04-05 Schaltung zur Erzeugung eines ausgeglichenen Puls-Pausenverhältnisses

Country Status (5)

Country Link
US (1) US5227671A (de)
EP (1) EP0565983B1 (de)
JP (1) JPH06283981A (de)
KR (1) KR930022717A (de)
DE (1) DE69323341T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397945A (en) * 1992-08-04 1995-03-14 Samsung Semiconductor, Inc. Duty cycle control circuit
US5546355A (en) * 1995-02-24 1996-08-13 Motorola, Inc. Integrated circuit memory having a self-timed write pulse independent of clock frequency and duty cycle
GB9522223D0 (en) * 1995-10-31 1996-01-03 Sgs Thomson Microelectronics A circuit for generating an output signal having a 50% duty cycle
US6578154B1 (en) 2000-01-10 2003-06-10 Research In Motion Limited Clock duty cycle correction circuit which corrects an input clock by directly comparing the input clock with a reference clock generated by the output clock
US6657464B1 (en) * 2002-04-25 2003-12-02 Applied Micro Circuits Corporation Method and circuit to reduce jitter generation in a PLL using a reference quadrupler, equalizer, and phase detector with control for multiple frequencies
US6741108B1 (en) * 2002-04-25 2004-05-25 Applied Micro Circuits Corporation Method and circuit to reduce jitter generation in a PLL using a reference quadrupler and an equalizer
JP2004350234A (ja) * 2003-05-26 2004-12-09 Seiko Epson Corp 半導体集積回路
US7102932B2 (en) * 2004-08-27 2006-09-05 Micron Technology, Inc. Input and output buffers having symmetrical operating characteristics and immunity from voltage variations
US7158067B2 (en) * 2005-01-31 2007-01-02 The United States Of America As Represented By The Secretary Of The Navy Analog to digital converter using sawtooth voltage signals with differential comparator
US20080136468A1 (en) * 2006-12-06 2008-06-12 Dandan Li Method and system for doubling phase-frequency detector comparison frequency for a fractional-n pll
US20080231335A1 (en) * 2007-03-20 2008-09-25 Honeywell International Inc. Circuit to reduce duty cycle distortion
US7969224B2 (en) * 2007-03-20 2011-06-28 Honeywell International, Inc. Circuit to reduce duty cycle distortion

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1048184A (en) * 1976-11-10 1979-02-06 Northern Telecom Limited Pulse duration correction circuit
US4360747A (en) * 1980-09-09 1982-11-23 Ampex Corporation Voltage controlled subcarrier phase shifter
JPS5757025A (en) * 1980-09-24 1982-04-06 Sony Corp Waveform converting circuit
JPS57115022A (en) * 1981-01-08 1982-07-17 Fuji Xerox Co Ltd Detecting circuit for zero cross point
US4634892A (en) * 1984-01-16 1987-01-06 National Semiconductor Corporation Pulse width modulator circuit for switching regulators
US4596954A (en) * 1984-02-29 1986-06-24 American Microsystems, Inc. Frequency doubler with fifty percent duty cycle output signal
LU86638A1 (de) * 1986-03-14 1987-04-02 Siemens Ag Schaltungsanordnung zur zeitregeneration von breitband-digitalsignalen

Also Published As

Publication number Publication date
EP0565983A1 (de) 1993-10-20
KR930022717A (ko) 1993-11-24
US5227671A (en) 1993-07-13
DE69323341D1 (de) 1999-03-18
EP0565983B1 (de) 1999-02-03
JPH06283981A (ja) 1994-10-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee