DE69100083D1 - Vorladeschaltung um einen speicher zu lesen. - Google Patents

Vorladeschaltung um einen speicher zu lesen.

Info

Publication number
DE69100083D1
DE69100083D1 DE9191402537T DE69100083T DE69100083D1 DE 69100083 D1 DE69100083 D1 DE 69100083D1 DE 9191402537 T DE9191402537 T DE 9191402537T DE 69100083 T DE69100083 T DE 69100083T DE 69100083 D1 DE69100083 D1 DE 69100083D1
Authority
DE
Germany
Prior art keywords
read
memory
precharge circuit
precharge
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE9191402537T
Other languages
English (en)
Other versions
DE69100083T2 (de
Inventor
Jean-Marie Gaultier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69100083D1 publication Critical patent/DE69100083D1/de
Publication of DE69100083T2 publication Critical patent/DE69100083T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
DE9191402537T 1990-09-25 1991-09-24 Vorladeschaltung um einen speicher zu lesen. Expired - Fee Related DE69100083T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9011817A FR2667193B1 (fr) 1990-09-25 1990-09-25 Circuit de precharge pour la lecture de memoires.

Publications (2)

Publication Number Publication Date
DE69100083D1 true DE69100083D1 (de) 1993-06-17
DE69100083T2 DE69100083T2 (de) 1993-08-26

Family

ID=9400634

Family Applications (1)

Application Number Title Priority Date Filing Date
DE9191402537T Expired - Fee Related DE69100083T2 (de) 1990-09-25 1991-09-24 Vorladeschaltung um einen speicher zu lesen.

Country Status (4)

Country Link
US (1) US5258955A (de)
EP (1) EP0478440B1 (de)
DE (1) DE69100083T2 (de)
FR (1) FR2667193B1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9423035D0 (en) * 1994-11-15 1995-01-04 Sgs Thomson Microelectronics Voltage boost circuit for a memory device
EP0936628A1 (de) * 1998-02-13 1999-08-18 STMicroelectronics S.r.l. Abtastverstärker für nichtflüchtigen Speicher mit niedriger Spannung
US7203096B2 (en) * 2005-06-30 2007-04-10 Infineon Technologies Flash Gmbh & Co. Kg Method and apparatus for sensing a state of a memory cell
CN101427320B (zh) * 2006-04-24 2011-10-05 Nxp股份有限公司 存储电路以及用于对存储元件进行读出的方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3932848A (en) * 1975-01-20 1976-01-13 Intel Corporation Feedback circuit for allowing rapid charging and discharging of a sense node in a static memory
JPS5712483A (en) * 1980-06-23 1982-01-22 Nec Corp Transistor circuit
FR2569054B1 (fr) * 1984-08-10 1986-11-28 Eurotechnique Sa Dispositif de neutralisation de l'acces a une zone a proteger d'un circuit integre
FR2587531B1 (fr) * 1985-04-26 1991-04-26 Eurotechnique Sa Memoire morte programmable electriquement une seule fois
JPS61273792A (ja) * 1985-05-28 1986-12-04 Toshiba Corp 半導体メモリ
JPH0713878B2 (ja) * 1985-06-20 1995-02-15 三菱電機株式会社 Ｃｍｏｓトランジスタ回路
US5012448A (en) * 1985-12-13 1991-04-30 Ricoh Company, Ltd. Sense amplifier for a ROM having a multilevel memory cell
FR2598852B1 (fr) * 1986-05-16 1988-10-21 Eurotechnique Sa Dispositif de protection d'entree pour circuits integres en technologie cmos.
FR2611972B1 (fr) * 1987-03-03 1989-05-19 Thomson Semiconducteurs Procede d'adressage d'elements redondants d'une memoire integree et dispositif permettant de mettre en oeuvre le procede
IT1232974B (it) * 1987-12-01 1992-03-11 Sgs Microelettronica Spa Circuito di polarizzazione e precarica per linea di bit di celle di memoria eprom in tecnologia cmos
JPH0727718B2 (ja) * 1988-02-19 1995-03-29 日本電気株式会社 センス回路
FR2629248B1 (fr) * 1988-03-25 1992-04-24 Sgs Thomson Microelectronics Procede de test de memoire a programmation unique et memoire correspondante
FR2636464B1 (fr) * 1988-09-14 1990-10-26 Sgs Thomson Microelectronics Memoire eprom avec signature interne concernant notamment le mode de programmation

Also Published As

Publication number Publication date
FR2667193B1 (fr) 1993-07-02
DE69100083T2 (de) 1993-08-26
US5258955A (en) 1993-11-02
EP0478440B1 (de) 1993-05-12
EP0478440A1 (de) 1992-04-01
FR2667193A1 (fr) 1992-03-27

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee