DE69033615D1 - Ätzen von Kontaktlöchern in einer dielektrischen Doppelschicht mit einer einzigen Ätzkammer - Google Patents

Ätzen von Kontaktlöchern in einer dielektrischen Doppelschicht mit einer einzigen Ätzkammer

Info

Publication number
DE69033615D1
DE69033615D1 DE69033615T DE69033615T DE69033615D1 DE 69033615 D1 DE69033615 D1 DE 69033615D1 DE 69033615 T DE69033615 T DE 69033615T DE 69033615 T DE69033615 T DE 69033615T DE 69033615 D1 DE69033615 D1 DE 69033615D1
Authority
DE
Germany
Prior art keywords
etch
double layer
contact holes
dielectric double
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033615T
Other languages
English (en)
Other versions
DE69033615T2 (de
Inventor
Valerie A Bach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69033615D1 publication Critical patent/DE69033615D1/de
Publication of DE69033615T2 publication Critical patent/DE69033615T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/009—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone characterised by the material treated
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/53—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone involving the removal of at least part of the materials of the treated article, e.g. etching, drying of hardened concrete
    • C04B41/5338—Etching
    • C04B41/5346—Dry etching
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/80—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone of only ceramics
    • C04B41/91—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone of only ceramics involving the removal of part of the materials of the treated articles, e.g. etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2111/00—Mortars, concrete or artificial stone or mixtures to prepare them, characterised by specific function, property or use
    • C04B2111/00474—Uses not provided for elsewhere in C04B2111/00
    • C04B2111/00844—Uses not provided for elsewhere in C04B2111/00 for electronic applications

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69033615T 1990-01-03 1990-12-27 Ätzen von Kontaktlöchern in einer dielektrischen Doppelschicht mit einer einzigen Ätzkammer Expired - Fee Related DE69033615T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/460,421 US4978420A (en) 1990-01-03 1990-01-03 Single chamber via etch through a dual-layer dielectric

Publications (2)

Publication Number Publication Date
DE69033615D1 true DE69033615D1 (de) 2000-09-28
DE69033615T2 DE69033615T2 (de) 2000-12-28

Family

ID=23828640

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033615T Expired - Fee Related DE69033615T2 (de) 1990-01-03 1990-12-27 Ätzen von Kontaktlöchern in einer dielektrischen Doppelschicht mit einer einzigen Ätzkammer

Country Status (4)

Country Link
US (1) US4978420A (de)
EP (1) EP0436387B1 (de)
JP (1) JPH04137751A (de)
DE (1) DE69033615T2 (de)

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US5780323A (en) 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5614756A (en) 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric
EP0509631A1 (de) * 1991-04-18 1992-10-21 Actel Corporation Antischmelzsicherungen mit minimalischen Oberflächen
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US5658425A (en) * 1991-10-16 1997-08-19 Lam Research Corporation Method of etching contact openings with reduced removal rate of underlying electrically conductive titanium silicide layer
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
US5294295A (en) * 1991-10-31 1994-03-15 Vlsi Technology, Inc. Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges
US5269880A (en) * 1992-04-03 1993-12-14 Northern Telecom Limited Tapering sidewalls of via holes
JP2988122B2 (ja) * 1992-05-14 1999-12-06 日本電気株式会社 ドライエッチング装置および半導体装置の製造方法
US5286344A (en) * 1992-06-15 1994-02-15 Micron Technology, Inc. Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride
US5880036A (en) 1992-06-15 1999-03-09 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
EP0592078A1 (de) * 1992-09-23 1994-04-13 Actel Corporation Antisicherung und Verfahren zu ihrer Herstellung
US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process
US5468339A (en) * 1992-10-09 1995-11-21 Advanced Micro Devices, Inc. Plasma etch process
US5391513A (en) * 1993-12-22 1995-02-21 Vlsi Technology, Inc. Wet/dry anti-fuse via etch
KR100366910B1 (ko) * 1994-04-05 2003-03-04 소니 가부시끼 가이샤 반도체장치의제조방법
US5493096A (en) * 1994-05-10 1996-02-20 Grumman Aerospace Corporation Thin substrate micro-via interconnect
TW295695B (de) * 1994-09-19 1997-01-11 Motorola Inc
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
US5621193A (en) * 1995-05-23 1997-04-15 Northrop Grumman Corporation Ceramic edge connect process
WO1996038861A1 (en) 1995-06-02 1996-12-05 Actel Corporation Raised tungsten plug antifuse and fabrication process
US5672242A (en) * 1996-01-31 1997-09-30 Integrated Device Technology, Inc. High selectivity nitride to oxide etch process
US5795833A (en) * 1996-08-01 1998-08-18 Taiwan Semiconductor Manufacturing Company, Ltd Method for fabricating passivation layers over metal lines
US5746884A (en) * 1996-08-13 1998-05-05 Advanced Micro Devices, Inc. Fluted via formation for superior metal step coverage
US5922622A (en) * 1996-09-03 1999-07-13 Vanguard International Semiconductor Corporation Pattern formation of silicon nitride
JP3323889B2 (ja) * 1996-10-28 2002-09-09 三菱電機株式会社 薄膜トランジスタの製造方法
US5972796A (en) * 1996-12-12 1999-10-26 Texas Instruments Incorporated In-situ barc and nitride etch process
DE19710401C1 (de) * 1997-03-13 1998-11-19 Bosch Gmbh Robert Verfahren zur Herstellung von Flüssigkristallzellen
US5952156A (en) * 1997-07-11 1999-09-14 Vanguard International Semiconductor Corporation Enhanced reflectivity coating (ERC) for narrow aperture width contact and interconnection lithography
US6051504A (en) * 1997-08-15 2000-04-18 International Business Machines Corporation Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma
US6165375A (en) * 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
KR100258875B1 (ko) * 1998-01-15 2000-06-15 김영환 다층배선용 비아형성방법
US6183940B1 (en) * 1998-03-17 2001-02-06 Integrated Device Technology, Inc. Method of retaining the integrity of a photoresist pattern
US6080676A (en) * 1998-09-17 2000-06-27 Advanced Micro Devices, Inc. Device and method for etching spacers formed upon an integrated circuit gate conductor
US6175087B1 (en) 1998-12-02 2001-01-16 International Business Machines Corporation Composite laminate circuit structure and method of forming the same
US6184119B1 (en) * 1999-03-15 2001-02-06 Vlsi Technology, Inc. Methods for reducing semiconductor contact resistance
US6461529B1 (en) 1999-04-26 2002-10-08 International Business Machines Corporation Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme
JP2001007468A (ja) * 1999-06-24 2001-01-12 Nec Kansai Ltd 配線基板，多層配線基板およびその製造方法
JP3387478B2 (ja) * 1999-06-30 2003-03-17 セイコーエプソン株式会社 半導体装置およびその製造方法
US6258729B1 (en) 1999-09-02 2001-07-10 Micron Technology, Inc. Oxide etching method and structures resulting from same
US6395639B1 (en) * 1999-09-16 2002-05-28 Agere Systems Guardian Corporation Process for improving line width variations between tightly spaced and isolated features in integrated circuits
US6649517B2 (en) * 2001-05-18 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Copper metal structure for the reduction of intra-metal capacitance
US6653214B1 (en) 2002-01-03 2003-11-25 The United States Of America As Represented By The Secretary Of The Air Force Measured via-hole etching
JP4668522B2 (ja) * 2003-03-31 2011-04-13 東京エレクトロン株式会社 プラズマ処理方法
WO2004090976A2 (en) * 2003-04-02 2004-10-21 Sun Microsystems, Inc. Optical communication between face-to-face semiconductor chips
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
JP5551887B2 (ja) * 2009-03-31 2014-07-16 ラピスセミコンダクタ株式会社 半導体素子の製造方法
CN101794712A (zh) * 2010-01-28 2010-08-04 中国科学院上海微系统与信息技术研究所 大角度离子注入抑制soi mos器件浮体效应的方法
EP2819162B1 (de) 2013-06-24 2020-06-17 IMEC vzw Verfahren zur Herstellung von Kontaktbereichen auf einem Halbleitersubstrat
US9257399B2 (en) * 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US11127825B2 (en) 2019-03-22 2021-09-21 International Business Machines Corporation Middle-of-line contacts with varying contact area providing reduced contact resistance

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Also Published As

Publication number Publication date
US4978420A (en) 1990-12-18
EP0436387B1 (de) 2000-08-23
DE69033615T2 (de) 2000-12-28
EP0436387A2 (de) 1991-07-10
EP0436387A3 (en) 1991-10-16
JPH04137751A (ja) 1992-05-12

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee