DE69033580T2 - Hysteresefreie supraleitende logische Schaltung - Google Patents

Hysteresefreie supraleitende logische Schaltung

Info

Publication number
DE69033580T2
DE69033580T2 DE69033580T DE69033580T DE69033580T2 DE 69033580 T2 DE69033580 T2 DE 69033580T2 DE 69033580 T DE69033580 T DE 69033580T DE 69033580 T DE69033580 T DE 69033580T DE 69033580 T2 DE69033580 T2 DE 69033580T2
Authority
DE
Germany
Prior art keywords
hysteresis
logic circuit
superconducting logic
free superconducting
free
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033580T
Other languages
English (en)
Other versions
DE69033580D1 (de
Inventor
Neal Joshua Schneier
Gerald Robert Ischer
Roger Alvernaz Davidheiser
George Earlin Avera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northrop Grumman Space and Mission Systems Corp
Original Assignee
TRW Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRW Inc filed Critical TRW Inc
Publication of DE69033580D1 publication Critical patent/DE69033580D1/de
Application granted granted Critical
Publication of DE69033580T2 publication Critical patent/DE69033580T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • H03K19/1952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with electro-magnetic coupling of the control current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/825—Apparatus per se, device per se, or process of making or operating same
    • Y10S505/856—Electrical transmission or interconnection system
    • Y10S505/857—Nonlinear solid-state device system or circuit
    • Y10S505/858—Digital logic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/825—Apparatus per se, device per se, or process of making or operating same
    • Y10S505/856—Electrical transmission or interconnection system
    • Y10S505/857—Nonlinear solid-state device system or circuit
    • Y10S505/865—Nonlinear solid-state device system or circuit with josephson junction

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)
DE69033580T 1989-12-29 1990-11-23 Hysteresefreie supraleitende logische Schaltung Expired - Fee Related DE69033580T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/459,220 US5051627A (en) 1989-12-29 1989-12-29 Superconducting nonhysteretic logic design

Publications (2)

Publication Number Publication Date
DE69033580D1 DE69033580D1 (de) 2000-08-10
DE69033580T2 true DE69033580T2 (de) 2001-03-08

Family

ID=23823890

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69033580T Expired - Fee Related DE69033580T2 (de) 1989-12-29 1990-11-23 Hysteresefreie supraleitende logische Schaltung
DE69031067T Expired - Fee Related DE69031067T2 (de) 1989-12-29 1990-11-23 Supraleitende logische Schaltung mit Hystereseverhalten

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69031067T Expired - Fee Related DE69031067T2 (de) 1989-12-29 1990-11-23 Supraleitende logische Schaltung mit Hystereseverhalten

Country Status (4)

Country Link
US (1) US5051627A (de)
EP (2) EP0435452B1 (de)
JP (2) JPH0413312A (de)
DE (2) DE69033580T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2645267B2 (ja) * 1990-03-13 1997-08-25 科学技術振興事業団 超電導論理回路
JPH03276493A (ja) * 1990-03-26 1991-12-06 Agency Of Ind Science & Technol ジョセフソン・メモリ回路
US5024993A (en) * 1990-05-02 1991-06-18 Microelectronics & Computer Technology Corporation Superconducting-semiconducting circuits, devices and systems
US5266844A (en) * 1991-07-15 1993-11-30 Hewlett-Packard Company Timing discriminator circuit and method for determining the arrival order of input signals
US5479131A (en) * 1992-11-09 1995-12-26 Hewlett-Packard Company Squid array voltage standard
DE19710039A1 (de) * 1997-03-12 1998-09-17 Joerg Oppenlaender Vorrichtung zur Erzeugung kohärenter Mikrowellen mit einem Netzwerk aus Josephsonkontakten (Selektor-Josephson-Netzwerk)
US6154044A (en) * 1998-11-20 2000-11-28 Trw Inc. Superconductive logic gate and random access memory
US6734699B1 (en) * 1999-07-14 2004-05-11 Northrop Grumman Corporation Self-clocked complementary logic
US6518786B2 (en) 2001-06-15 2003-02-11 Trw Inc. Combinational logic using asynchronous single-flux quantum gates
US7002366B2 (en) * 2003-08-20 2006-02-21 Northrop Grumman Corporation Superconducting constant current source
US20050062131A1 (en) * 2003-09-24 2005-03-24 Murduck James Matthew A1/A1Ox/A1 resistor process for integrated circuits
US7468630B2 (en) * 2006-08-25 2008-12-23 Hypres, Inc. Superconducting switching amplifier
GB2457706B (en) * 2008-02-22 2010-03-10 Siemens Magnet Technology Ltd Coil energisation apparatus and method of energising a superconductive coil
US8571614B1 (en) 2009-10-12 2013-10-29 Hypres, Inc. Low-power biasing networks for superconducting integrated circuits
US9509315B2 (en) 2013-03-11 2016-11-29 Massachusetts Institute Of Technology Superconducting three-terminal device and logic gates
WO2016171875A1 (en) 2015-04-03 2016-10-27 Massachusetts Institute Of Technology Current crowding in three-terminal superconducting devices and related methods
US10222416B1 (en) 2015-04-14 2019-03-05 Hypres, Inc. System and method for array diagnostics in superconducting integrated circuit
US10122350B2 (en) 2015-11-17 2018-11-06 Northrop Grumman Systems Corporation Josephson transmission line (JTL) system
US11211722B2 (en) 2017-03-09 2021-12-28 Microsoft Technology Licensing, Llc Superconductor interconnect system
US10122351B1 (en) 2017-07-25 2018-11-06 Northrop Grumman Systems Corporation Superconducting bi-directional current driver
US10491178B2 (en) 2017-10-31 2019-11-26 Northrop Grumman Systems Corporation Parametric amplifier system
US10090841B1 (en) 2018-02-02 2018-10-02 Northrop Grumman Systems Corporation Josephson polarity and logical inverter gates
US11200947B2 (en) 2018-02-05 2021-12-14 Massachusetts Institute Of Technology Superconducting nanowire-based programmable processor
US10122352B1 (en) 2018-05-07 2018-11-06 Northrop Grumman Systems Corporation Current driver system
CN110739010B (zh) * 2019-10-21 2021-05-11 中国科学院上海微系统与信息技术研究所 低温存储单元及存储器件

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3843895A (en) * 1973-06-29 1974-10-22 Ibm Two-way or circuit using josephson tunnelling technology
CH559481A5 (de) * 1973-12-13 1975-02-28 Ibm
JPS6010451B2 (ja) * 1979-08-27 1985-03-18 工業技術院長 ジヨゼフソン効果を利用したスイツチング回路
EP0035350B1 (de) * 1980-02-20 1984-01-25 Fujitsu Limited Supraleitende logische Vorrichtung mit einem Josephson-Kontakt
JPS57203318A (en) * 1981-06-10 1982-12-13 Hitachi Ltd Superconductive digital circuit
JPS5846725A (ja) * 1981-09-11 1983-03-18 Nippon Telegr & Teleph Corp <Ntt> 超伝導論理回路
JPS58108830A (ja) * 1981-12-23 1983-06-29 Hitachi Ltd ジヨセフソン論理集積回路
JPS59143427A (ja) * 1983-02-04 1984-08-17 Rikagaku Kenkyusho 超伝導磁束量子論理演算回路
JPS60254913A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd ジヨセフソン自己ゲ−ト回路
JPS6182533A (ja) * 1984-09-28 1986-04-26 Heihachiro Hirai インバ−タ
DE68906044T2 (de) * 1988-02-10 1993-11-04 Sharp Kk Supraleitende logische vorrichtung.
JPH01278123A (ja) * 1988-04-30 1989-11-08 Sharp Corp 相補型超電導回路

Also Published As

Publication number Publication date
EP0435452B1 (de) 1997-07-16
EP0766401B1 (de) 2000-07-05
EP0435452A3 (en) 1991-09-18
DE69033580D1 (de) 2000-08-10
EP0766401A1 (de) 1997-04-02
DE69031067T2 (de) 1997-11-06
JPH07307092A (ja) 1995-11-21
US5051627A (en) 1991-09-24
DE69031067D1 (de) 1997-08-21
JP2672479B2 (ja) 1997-11-05
EP0435452A2 (de) 1991-07-03
JPH0413312A (ja) 1992-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee