DE69032915T2 - VLSI Schaltung mit von einem benachbarten angepassten Taktgenerator gesteuerten Verriegelungsschaltungen - Google Patents

VLSI Schaltung mit von einem benachbarten angepassten Taktgenerator gesteuerten Verriegelungsschaltungen

Info

Publication number
DE69032915T2
DE69032915T2 DE69032915T DE69032915T DE69032915T2 DE 69032915 T2 DE69032915 T2 DE 69032915T2 DE 69032915 T DE69032915 T DE 69032915T DE 69032915 T DE69032915 T DE 69032915T DE 69032915 T2 DE69032915 T2 DE 69032915T2
Authority
DE
Germany
Prior art keywords
clock generator
latch circuits
vlsi circuit
circuits controlled
matched clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032915T
Other languages
English (en)
Other versions
DE69032915D1 (de
Inventor
William A Samaras
David T Vaughan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE69032915D1 publication Critical patent/DE69032915D1/de
Application granted granted Critical
Publication of DE69032915T2 publication Critical patent/DE69032915T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
DE69032915T 1989-06-09 1990-06-11 VLSI Schaltung mit von einem benachbarten angepassten Taktgenerator gesteuerten Verriegelungsschaltungen Expired - Fee Related DE69032915T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/363,708 US5072132A (en) 1989-06-09 1989-06-09 Vsli latch system and sliver pulse generator with high correlation factor

Publications (2)

Publication Number Publication Date
DE69032915D1 DE69032915D1 (de) 1999-03-11
DE69032915T2 true DE69032915T2 (de) 1999-09-16

Family

ID=23431370

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032915T Expired - Fee Related DE69032915T2 (de) 1989-06-09 1990-06-11 VLSI Schaltung mit von einem benachbarten angepassten Taktgenerator gesteuerten Verriegelungsschaltungen

Country Status (7)

Country Link
US (1) US5072132A (de)
EP (1) EP0401865B1 (de)
JP (1) JP2579237B2 (de)
KR (1) KR930008418B1 (de)
AU (1) AU631428B2 (de)
CA (1) CA2017707A1 (de)
DE (1) DE69032915T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5303350A (en) * 1990-12-20 1994-04-12 Acer Incorporated Circuit for initializing registers using two input signals for writing default value into D-latch after a reset operation
US5175515A (en) * 1991-06-21 1992-12-29 Compaq Computer Corporation Signal routing technique for electronic systems
US5552737A (en) * 1994-07-11 1996-09-03 International Business Machines Corporation Scannable master slave latch actuated by single phase clock
US5642068A (en) * 1994-08-08 1997-06-24 Mosaid Technologies Incorporated Clock period dependent pulse generator
US6115836A (en) * 1997-09-17 2000-09-05 Cypress Semiconductor Corporation Scan path circuitry for programming a variable clock pulse width
US6229750B1 (en) 1999-09-30 2001-05-08 International Business Machines Corporation Method and system for reducing power dissipation in a semiconductor storage device
US6609228B1 (en) 2000-11-15 2003-08-19 International Business Machines Corporation Latch clustering for power optimization
US6621302B2 (en) 2001-03-21 2003-09-16 Bae Systems Information And Electronic Systems Integration, Inc Efficient sequential circuits using critical race control
US7634749B1 (en) * 2005-04-01 2009-12-15 Cadence Design Systems, Inc. Skew insensitive clocking method and apparatus
US7694242B1 (en) * 2006-12-11 2010-04-06 Cadence Design Systems, Inc. System and method of replacing flip-flops with pulsed latches in circuit designs
US7746137B2 (en) 2007-08-28 2010-06-29 Qualcomm Incorporated Sequential circuit element including a single clocked transistor
US7724058B2 (en) * 2007-10-31 2010-05-25 Qualcomm Incorporated Latch structure and self-adjusting pulse generator using the latch
US9564881B2 (en) 2015-05-22 2017-02-07 Qualcomm Incorporated Area-efficient metal-programmable pulse latch design
US9979394B2 (en) 2016-02-16 2018-05-22 Qualcomm Incorporated Pulse-generator

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57112129A (en) * 1980-12-27 1982-07-13 Yamatake Honeywell Co Ltd Latch circuit
JPS585022A (ja) * 1981-07-02 1983-01-12 Nec Corp 前縁微分回路
US4425514A (en) * 1981-11-10 1984-01-10 Rca Corporation Fixed pulse width, fast recovery one-shot pulse generator
JPS59104820A (ja) * 1982-12-08 1984-06-16 Hitachi Ltd フリツプフロツプ回路
US4570082A (en) * 1983-11-25 1986-02-11 International Business Machines Corporation Single clocked latch circuit
FR2556903B1 (fr) * 1983-12-15 1986-04-11 Telediffusion Fse Procede et circuits de regeneration d'instants significatifs d'un signal periodique
JPS60261211A (ja) * 1984-06-08 1985-12-24 Nec Corp マスタ−・スレ−ブ型フリツプ・フロツプ
JPH0630377B2 (ja) * 1984-06-15 1994-04-20 株式会社日立製作所 半導体集積回路装置
US4701860A (en) * 1985-03-07 1987-10-20 Harris Corporation Integrated circuit architecture formed of parametric macro-cells
US4733111A (en) * 1985-07-17 1988-03-22 CSELT--Centro Studi e Laboratori Telecomunicazioni S.p.A. Sequential-logic basic element in CMOS technology operating by a single clock signal
CA1275310C (en) * 1985-11-26 1990-10-16 Katuhisa Kubota Master slave latch circuit
US4797575A (en) * 1986-12-05 1989-01-10 Western Digital Corporation Flip-flop with identical propagation delay in clock pass through mode and in normal operation
US4786829A (en) * 1987-02-24 1988-11-22 Letcher John H Latched fedback memory finite-state-engine
JPH0828421B2 (ja) * 1987-08-27 1996-03-21 株式会社東芝 半導体集積回路装置
JPS6460015A (en) * 1987-08-31 1989-03-07 Fujitsu Ltd Flip flop circuit
US4864161A (en) * 1988-05-05 1989-09-05 Altera Corporation Multifunction flip-flop-type circuit

Also Published As

Publication number Publication date
AU5596390A (en) 1990-12-13
CA2017707A1 (en) 1990-12-09
DE69032915D1 (de) 1999-03-11
KR930008418B1 (ko) 1993-08-31
EP0401865A2 (de) 1990-12-12
KR910001964A (ko) 1991-01-31
JPH0326104A (ja) 1991-02-04
AU631428B2 (en) 1992-11-26
US5072132A (en) 1991-12-10
JP2579237B2 (ja) 1997-02-05
EP0401865B1 (de) 1999-01-27
EP0401865A3 (de) 1993-07-07

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee