DE69025233D1 - Vorlade-Architektur von integrierten Speichern - Google Patents

Vorlade-Architektur von integrierten Speichern

Info

Publication number
DE69025233D1
DE69025233D1 DE69025233T DE69025233T DE69025233D1 DE 69025233 D1 DE69025233 D1 DE 69025233D1 DE 69025233 T DE69025233 T DE 69025233T DE 69025233 T DE69025233 T DE 69025233T DE 69025233 D1 DE69025233 D1 DE 69025233D1
Authority
DE
Germany
Prior art keywords
preload
architecture
integrated memories
memories
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69025233T
Other languages
German (de)
English (en)
Inventor
Michael Kevin Ciraula
Christopher Mccall Durham
Reginald Eric Harrison
Derwin L Jallice
Dave Christopher Lawson
Craig Lee Stephen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69025233D1 publication Critical patent/DE69025233D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69025233T 1989-06-23 1990-02-16 Vorlade-Architektur von integrierten Speichern Expired - Lifetime DE69025233D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/370,941 US4969125A (en) 1989-06-23 1989-06-23 Asynchronous segmented precharge architecture

Publications (1)

Publication Number Publication Date
DE69025233D1 true DE69025233D1 (de) 1996-03-21

Family

ID=23461830

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025233T Expired - Lifetime DE69025233D1 (de) 1989-06-23 1990-02-16 Vorlade-Architektur von integrierten Speichern

Country Status (4)

Country Link
US (1) US4969125A (enExample)
EP (1) EP0405055B1 (enExample)
JP (1) JPH07101555B2 (enExample)
DE (1) DE69025233D1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0474384A (ja) * 1990-07-17 1992-03-09 Toshiba Corp 半導体集積回路装置
JP2630059B2 (ja) * 1990-11-09 1997-07-16 日本電気株式会社 半導体メモリ装置
US5307142A (en) * 1991-11-15 1994-04-26 The United States Of America As Represented By The United States Department Of Energy High performance static latches with complete single event upset immunity
KR930010990A (ko) * 1991-11-19 1993-06-23 김광호 반도체 메모리 장치에서의 스피드 향상을 위한 회로
KR940016288A (ko) * 1992-12-25 1994-07-22 오가 노리오 반도체메모리 및 그 선별방법
GB2277390B (en) * 1993-04-21 1997-02-26 Plessey Semiconductors Ltd Random access memory
US5592426A (en) * 1993-10-29 1997-01-07 International Business Machines Corporation Extended segmented precharge architecture
JPH07230691A (ja) * 1994-02-16 1995-08-29 Fujitsu Ltd 半導体記憶装置
JP3497650B2 (ja) * 1996-02-27 2004-02-16 株式会社東芝 半導体メモリ装置
US6181641B1 (en) 1999-05-26 2001-01-30 Lockheed Martin Corporation Memory device having reduced power requirements and associated methods
KR100334574B1 (ko) * 2000-01-31 2002-05-03 윤종용 풀-페이지 모드를 갖는 버스트-타입의 반도체 메모리 장치
US6480419B2 (en) * 2001-02-22 2002-11-12 Samsung Electronics Co., Ltd. Bit line setup and discharge circuit for programming non-volatile memory
US6430099B1 (en) 2001-05-11 2002-08-06 Broadcom Corporation Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation
KR100443910B1 (ko) * 2001-12-17 2004-08-09 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 메모리 셀 억세스 방법
US6778455B2 (en) * 2002-07-24 2004-08-17 Micron Technology, Inc. Method and apparatus for saving refresh current
US8437213B2 (en) * 2008-01-03 2013-05-07 Texas Instruments Incorporated Characterization of bits in a functional memory
TWI423256B (zh) * 2008-10-29 2014-01-11 Etron Technology Inc 資料感測裝置與方法
US20140219007A1 (en) * 2013-02-07 2014-08-07 Nvidia Corporation Dram with segmented page configuration
US11361819B2 (en) * 2017-12-14 2022-06-14 Advanced Micro Devices, Inc. Staged bitline precharge
US11264070B2 (en) 2020-01-16 2022-03-01 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for memory operation using local word lines

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589285A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 半導体装置
FR2528613B1 (fr) * 1982-06-09 1991-09-20 Hitachi Ltd Memoire a semi-conducteurs
JPS59121688A (ja) * 1982-12-28 1984-07-13 Toshiba Corp スタテイツクランダムアクセスメモリ−
US4602354A (en) * 1983-01-10 1986-07-22 Ncr Corporation X-and-OR memory array
JPH0670880B2 (ja) * 1983-01-21 1994-09-07 株式会社日立マイコンシステム 半導体記憶装置
JPS59178685A (ja) * 1983-03-30 1984-10-09 Toshiba Corp 半導体記憶回路
US4520465A (en) * 1983-05-05 1985-05-28 Motorola, Inc. Method and apparatus for selectively precharging column lines of a memory
JPS60179993A (ja) * 1984-02-27 1985-09-13 Toshiba Corp ランダムアクセスメモリ
JPS6150284A (ja) * 1984-08-17 1986-03-12 Mitsubishi Electric Corp シエアドセンスアンプ回路の駆動方法
US4594689A (en) * 1984-09-04 1986-06-10 Motorola, Inc. Circuit for equalizing bit lines in a ROM
US4633442A (en) * 1985-02-04 1986-12-30 Raytheon Company Protective circuitry for a read only memory
JPH0750554B2 (ja) * 1985-09-06 1995-05-31 株式会社東芝 スタテイツク型メモリ
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
JPH0664907B2 (ja) * 1985-06-26 1994-08-22 株式会社日立製作所 ダイナミツク型ｒａｍ
US4742487A (en) * 1986-04-15 1988-05-03 International Business Machines Corporation Inhibit and transfer circuitry for memory cell being read from multiple ports

Also Published As

Publication number Publication date
JPH0334189A (ja) 1991-02-14
EP0405055A3 (enExample) 1994-03-30
EP0405055B1 (en) 1996-02-07
JPH07101555B2 (ja) 1995-11-01
EP0405055A2 (en) 1991-01-02
US4969125A (en) 1990-11-06

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Legal Events

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8332 No legal effect for de