DE69022860T2 - Prüfmodusumschaltsystem für LSI. - Google Patents

Prüfmodusumschaltsystem für LSI.

Info

Publication number
DE69022860T2
DE69022860T2 DE69022860T DE69022860T DE69022860T2 DE 69022860 T2 DE69022860 T2 DE 69022860T2 DE 69022860 T DE69022860 T DE 69022860T DE 69022860 T DE69022860 T DE 69022860T DE 69022860 T2 DE69022860 T2 DE 69022860T2
Authority
DE
Germany
Prior art keywords
lsi
mode switching
test mode
switching system
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69022860T
Other languages
English (en)
Other versions
DE69022860D1 (de
Inventor
Nobuyuki Horie
Toshihiro Yamanaka
Daiji Yamane
Noriaki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69022860D1 publication Critical patent/DE69022860D1/de
Publication of DE69022860T2 publication Critical patent/DE69022860T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69022860T 1989-01-06 1990-01-03 Prüfmodusumschaltsystem für LSI. Expired - Lifetime DE69022860T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1001520A JPH02181677A (ja) 1989-01-06 1989-01-06 Ｌｓｉのテストモード切替方式

Publications (2)

Publication Number Publication Date
DE69022860D1 DE69022860D1 (de) 1995-11-16
DE69022860T2 true DE69022860T2 (de) 1996-05-30

Family

ID=11503777

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022860T Expired - Lifetime DE69022860T2 (de) 1989-01-06 1990-01-03 Prüfmodusumschaltsystem für LSI.

Country Status (4)

Country Link
US (1) US5144627A (de)
EP (1) EP0377455B1 (de)
JP (1) JPH02181677A (de)
DE (1) DE69022860T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682325B2 (ja) * 1990-05-29 1994-10-19 株式会社東芝 情報処理装置のテスト容易化回路
JPH0455778A (ja) * 1990-06-26 1992-02-24 Toshiba Corp 半導体装置のテスト方法
US5130988A (en) * 1990-09-17 1992-07-14 Northern Telecom Limited Software verification by fault insertion
US6018812A (en) * 1990-10-17 2000-01-25 501 Charles Stark Draper Laboratory, Inc. Reliable wafer-scale integrated computing systems
JPH05302961A (ja) * 1991-03-27 1993-11-16 Nec Corp Ｌｓｉに於けるテスト信号出力回路
US5850509A (en) * 1991-11-13 1998-12-15 Intel Corporation Circuitry for propagating test mode signals associated with a memory array
US5357615A (en) * 1991-12-19 1994-10-18 Intel Corporation Addressing control signal configuration in a computer system
US5455517A (en) * 1992-06-09 1995-10-03 International Business Machines Corporation Data output impedance control
JPH07225261A (ja) * 1994-02-09 1995-08-22 Advantest Corp 半導体試験装置用パターン発生器
FR2753274B1 (fr) * 1996-09-10 1998-11-27 Sgs Thomson Microelectronics Circuit comprenant des moyens de test structurel sans plot de test dedie au test
US6075396A (en) * 1998-06-18 2000-06-13 S3 Incorporated Using power-on mode to control test mode
JP3293813B2 (ja) * 1999-11-25 2002-06-17 エヌイーシーマイクロシステム株式会社 通信用ｌｓｉ
JP3509001B2 (ja) 1999-12-07 2004-03-22 松下電器産業株式会社 自己診断テスト回路機能を備えた半導体集積回路および半導体集積回路のテスト方法
JP2007322150A (ja) * 2006-05-30 2007-12-13 Matsushita Electric Ind Co Ltd 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58144954A (ja) * 1982-02-24 1983-08-29 Fujitsu Ltd 診断方式
US4546472A (en) * 1983-01-27 1985-10-08 Intel Corporation Method and means for testing integrated circuits
JPS59160778A (ja) * 1983-03-04 1984-09-11 Nec Corp 試験回路
JPS61100673A (ja) * 1984-10-23 1986-05-19 Mitsubishi Electric Corp 論理回路の試験制御回路
JPS61181978A (ja) * 1985-02-08 1986-08-14 Hitachi Ltd 集積回路装置
JPS61191973A (ja) * 1985-02-20 1986-08-26 Fujitsu Ltd 試験回路をそなえた半導体集積回路
JPS61258399A (ja) * 1985-05-11 1986-11-15 Fujitsu Ltd 半導体集積回路装置
JPH0691140B2 (ja) * 1986-07-11 1994-11-14 日本電気株式会社 半導体集積回路
JPS6337270A (ja) * 1986-07-31 1988-02-17 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
EP0377455A3 (de) 1991-10-23
US5144627A (en) 1992-09-01
DE69022860D1 (de) 1995-11-16
EP0377455B1 (de) 1995-10-11
JPH02181677A (ja) 1990-07-16
EP0377455A2 (de) 1990-07-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

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