DE68928286D1 - Verfahren zur Bildung einer Schicht aus P-Typ-Germanium auf einem Körper aus Gallium-Arsenid - Google Patents

Verfahren zur Bildung einer Schicht aus P-Typ-Germanium auf einem Körper aus Gallium-Arsenid

Info

Publication number
DE68928286D1
DE68928286D1 DE68928286T DE68928286T DE68928286D1 DE 68928286 D1 DE68928286 D1 DE 68928286D1 DE 68928286 T DE68928286 T DE 68928286T DE 68928286 T DE68928286 T DE 68928286T DE 68928286 D1 DE68928286 D1 DE 68928286D1
Authority
DE
Germany
Prior art keywords
forming
layer
gallium arsenide
type germanium
arsenide body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928286T
Other languages
English (en)
Other versions
DE68928286T2 (de
Inventor
Masafumi C O Nec Corp Kawanaka
Tooru C O Nec Corporati Kimura
Jun Ichi C O Nec Corporat Sone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE68928286D1 publication Critical patent/DE68928286D1/de
Application granted granted Critical
Publication of DE68928286T2 publication Critical patent/DE68928286T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/041—Doping control in crystal growth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/916—Autodoping control or utilization
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE68928286T 1988-03-25 1989-03-28 Verfahren zur Bildung einer Schicht aus P-Typ-Germanium auf einem Körper aus Gallium-Arsenid Expired - Fee Related DE68928286T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7233688 1988-03-25
JP63304387A JP2764966B2 (ja) 1988-03-25 1988-11-30 ヘテロ構造バイポーラ・トランジスタと分子線エピタキシャル成長法

Publications (2)

Publication Number Publication Date
DE68928286D1 true DE68928286D1 (de) 1997-10-09
DE68928286T2 DE68928286T2 (de) 1998-01-15

Family

ID=26413469

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928286T Expired - Fee Related DE68928286T2 (de) 1988-03-25 1989-03-28 Verfahren zur Bildung einer Schicht aus P-Typ-Germanium auf einem Körper aus Gallium-Arsenid

Country Status (4)

Country Link
US (1) US5047365A (de)
EP (1) EP0334682B1 (de)
JP (1) JP2764966B2 (de)
DE (1) DE68928286T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5183778A (en) * 1989-11-20 1993-02-02 Fujitsu Limited Method of producing a semiconductor device
US5420052A (en) * 1994-04-19 1995-05-30 Texas Instruments Incorporated Method of fabricating a semiplanar heterojunction bipolar transistor
US5583059A (en) * 1994-06-01 1996-12-10 International Business Machines Corporation Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI
FR2737734B1 (fr) * 1995-08-10 1997-08-29 Alcatel Optronics Procede de gravure d'un substrat par jets chimiques
US6723621B1 (en) * 1997-06-30 2004-04-20 International Business Machines Corporation Abrupt delta-like doping in Si and SiGe films by UHV-CVD
DE19824110A1 (de) * 1998-05-29 1999-12-09 Daimler Chrysler Ag Resonanz Phasen Transistor mit Laufzeitverzögerung
US6743680B1 (en) 2000-06-22 2004-06-01 Advanced Micro Devices, Inc. Process for manufacturing transistors having silicon/germanium channel regions
US6709935B1 (en) 2001-03-26 2004-03-23 Advanced Micro Devices, Inc. Method of locally forming a silicon/geranium channel layer
US6870204B2 (en) 2001-11-21 2005-03-22 Astralux, Inc. Heterojunction bipolar transistor containing at least one silicon carbide layer
EP2518264B1 (de) * 2004-11-19 2014-04-09 Halliburton Energy Services, Inc. Verfahren und Vorrichtung zum Bohren, Abschließen und Konfigurieren von U-Rohrbohrlöchern
DE102011004411B4 (de) * 2011-02-18 2017-02-23 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Siliziumbasierter Heterobipolartransistor mit einer Kollektorschicht aus einem III-V-Halbleiter
US20130048061A1 (en) * 2011-08-24 2013-02-28 International Business Machines Corporation Monolithic multi-junction photovoltaic cell and method
US9653298B2 (en) 2013-01-14 2017-05-16 Ipg Photonics Corporation Thermal processing by transmission of mid infra-red laser light through semiconductor substrate
RU2556765C1 (ru) * 2014-02-25 2015-07-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования Кабардино-Балкарский государственный университет им. Х.М. Бербекова Способ изготовления полупроводниковой структуры
RU2629659C1 (ru) * 2016-11-22 2017-08-30 Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) Способ изготовления полупроводникового прибора
US11488889B1 (en) * 2017-08-08 2022-11-01 Northrop Grumman Systems Corporation Semiconductor device passive thermal management

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4188710A (en) * 1978-08-11 1980-02-19 The United States Of America As Represented By The Secretary Of The Navy Ohmic contacts for group III-V n-type semiconductors using epitaxial germanium films
US4261771A (en) * 1979-10-31 1981-04-14 Bell Telephone Laboratories, Incorporated Method of fabricating periodic monolayer semiconductor structures by molecular beam epitaxy
US4398963A (en) * 1980-11-19 1983-08-16 The United States Of America As Represented By The Secretary Of The Navy Method for making non-alloyed heterojunction ohmic contacts
US4716445A (en) * 1986-01-17 1987-12-29 Nec Corporation Heterojunction bipolar transistor having a base region of germanium

Also Published As

Publication number Publication date
US5047365A (en) 1991-09-10
EP0334682A2 (de) 1989-09-27
JP2764966B2 (ja) 1998-06-11
EP0334682A3 (de) 1991-11-27
EP0334682B1 (de) 1997-09-03
DE68928286T2 (de) 1998-01-15
JPH02138743A (ja) 1990-05-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee