DE68925813D1 - Verfahren und vorrichtung zum nachweis von fehlern in halbleiterschaltungen - Google Patents

Verfahren und vorrichtung zum nachweis von fehlern in halbleiterschaltungen

Info

Publication number
DE68925813D1
DE68925813D1 DE68925813T DE68925813T DE68925813D1 DE 68925813 D1 DE68925813 D1 DE 68925813D1 DE 68925813 T DE68925813 T DE 68925813T DE 68925813 T DE68925813 T DE 68925813T DE 68925813 D1 DE68925813 D1 DE 68925813D1
Authority
DE
Germany
Prior art keywords
semiconductor circuits
detecting faults
faults
detecting
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68925813T
Other languages
English (en)
Other versions
DE68925813T2 (de
Inventor
Tushar Gheewala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CROSSCHECK TECHNOLOGY Inc A DE
Original Assignee
CROSSCHECK TECHNOLOGY Inc A DE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CROSSCHECK TECHNOLOGY Inc A DE filed Critical CROSSCHECK TECHNOLOGY Inc A DE
Publication of DE68925813D1 publication Critical patent/DE68925813D1/de
Application granted granted Critical
Publication of DE68925813T2 publication Critical patent/DE68925813T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE68925813T 1988-09-09 1989-09-06 Verfahren und vorrichtung zum nachweis von fehlern in halbleiterschaltungen Expired - Fee Related DE68925813T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/242,848 US4937826A (en) 1988-09-09 1988-09-09 Method and apparatus for sensing defects in integrated circuit elements
PCT/US1989/003843 WO1990002997A1 (en) 1988-09-09 1989-09-06 Method and apparatus for sensing defects in integrated circuit elements

Publications (2)

Publication Number Publication Date
DE68925813D1 true DE68925813D1 (de) 1996-04-04
DE68925813T2 DE68925813T2 (de) 1996-08-08

Family

ID=22916409

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68925813T Expired - Fee Related DE68925813T2 (de) 1988-09-09 1989-09-06 Verfahren und vorrichtung zum nachweis von fehlern in halbleiterschaltungen

Country Status (5)

Country Link
US (1) US4937826A (de)
EP (1) EP0396660B1 (de)
JP (1) JPH03501889A (de)
DE (1) DE68925813T2 (de)
WO (1) WO1990002997A1 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
US5056094A (en) * 1989-06-09 1991-10-08 Texas Instruments Incorporated Delay fault testing method and apparatus
JP3005250B2 (ja) * 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US5038349A (en) * 1989-08-25 1991-08-06 Cross-Check Technology, Inc. Method for reducing masking of errors when using a grid-based, "cross-check" test structure
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
US5202624A (en) * 1990-08-31 1993-04-13 Cross-Check Technology, Inc. Interface between ic operational circuitry for coupling test signal from internal test matrix
JP2925287B2 (ja) * 1990-10-17 1999-07-28 富士通株式会社 半導体装置
US5230001A (en) * 1991-03-08 1993-07-20 Crosscheck Technology, Inc. Method for testing a sequential circuit by splicing test vectors into sequential test pattern
JP2884847B2 (ja) * 1991-10-03 1999-04-19 三菱電機株式会社 故障検出機能を備えた半導体集積回路装置の製造方法
EP0562886B1 (de) * 1992-03-27 2004-05-12 Matsushita Electric Industrial Co., Ltd. Verfahren und Gerät zur Prüfsequenzgenerierung
US5442282A (en) * 1992-07-02 1995-08-15 Lsi Logic Corporation Testing and exercising individual, unsingulated dies on a wafer
US5389556A (en) * 1992-07-02 1995-02-14 Lsi Logic Corporation Individually powering-up unsingulated dies on a wafer
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5428621A (en) * 1992-09-21 1995-06-27 Sundisk Corporation Latent defect handling in EEPROM devices
US5452309A (en) * 1992-12-18 1995-09-19 Amdahl Corporation Apparatus and method for forcing hardware errors via scan
US5414715A (en) * 1993-02-05 1995-05-09 Genrad, Inc. Method for automatic open-circuit detection
JP3124417B2 (ja) * 1993-07-13 2001-01-15 三菱電機株式会社 論理シミュレーションシステム及び論理シミュレーション方法
JPH07159496A (ja) * 1993-10-12 1995-06-23 At & T Global Inf Solutions Internatl Inc 集積回路の検査のための装置及びその方法
US5459738A (en) * 1994-01-26 1995-10-17 Watari; Hiromichi Apparatus and method for digital circuit testing
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
US5546408A (en) * 1994-06-09 1996-08-13 International Business Machines Corporation Hierarchical pattern faults for describing logic circuit failure mechanisms
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
JP3137030B2 (ja) * 1997-04-18 2001-02-19 日本電気株式会社 半導体装置
US5936876A (en) * 1997-12-03 1999-08-10 Lsi Logic Corporation Semiconductor integrated circuit core probing for failure analysis
US6148425A (en) * 1998-02-12 2000-11-14 Lucent Technologies Inc. Bist architecture for detecting path-delay faults in a sequential circuit
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US8051352B2 (en) 2006-04-27 2011-11-01 Mentor Graphics Corporation Timing-aware test generation and fault simulation
US9264187B1 (en) * 2014-10-09 2016-02-16 Intel Corporation Measuring bit error rate during runtime of a receiver circuit
JP6686282B2 (ja) * 2015-03-16 2020-04-22 セイコーエプソン株式会社 回路装置、物理量検出装置、電子機器及び移動体
US9941881B1 (en) * 2017-03-23 2018-04-10 Qualcomm Incorporated Apparatus and method for latching data including AND-NOR or OR-NAND gate and feedback paths

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3380105D1 (en) * 1982-09-29 1989-07-27 Hitachi Ltd Semiconductor integrated circuit device
JPS59121688A (ja) * 1982-12-28 1984-07-13 Toshiba Corp スタテイツクランダムアクセスメモリ−
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法
US4672610A (en) * 1985-05-13 1987-06-09 Motorola, Inc. Built in self test input generator for programmable logic arrays
US4739250A (en) * 1985-11-20 1988-04-19 Fujitsu Limited Semiconductor integrated circuit device with test circuit
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits

Also Published As

Publication number Publication date
JPH03501889A (ja) 1991-04-25
EP0396660A1 (de) 1990-11-14
EP0396660A4 (en) 1992-08-05
WO1990002997A1 (en) 1990-03-22
EP0396660B1 (de) 1996-02-28
DE68925813T2 (de) 1996-08-08
US4937826A (en) 1990-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee