DE69533567D1 - Vorrichtung und Verfahren zum Auffinden von False-Timing-Paths in digitalen Schaltkreisen - Google Patents

Vorrichtung und Verfahren zum Auffinden von False-Timing-Paths in digitalen Schaltkreisen

Info

Publication number
DE69533567D1
DE69533567D1 DE69533567T DE69533567T DE69533567D1 DE 69533567 D1 DE69533567 D1 DE 69533567D1 DE 69533567 T DE69533567 T DE 69533567T DE 69533567 T DE69533567 T DE 69533567T DE 69533567 D1 DE69533567 D1 DE 69533567D1
Authority
DE
Germany
Prior art keywords
digital circuits
timing paths
false timing
finding false
finding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69533567T
Other languages
English (en)
Other versions
DE69533567T2 (de
Inventor
Ramachandra P Kunda
Saied Bozorgui-Nesbat
Hong Hao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69533567D1 publication Critical patent/DE69533567D1/de
Publication of DE69533567T2 publication Critical patent/DE69533567T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318328—Generation of test inputs, e.g. test vectors, patterns or sequences for delay tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69533567T 1994-08-09 1995-07-27 Vorrichtung und Verfahren zum Auffinden von False-Timing-Paths in digitalen Schaltkreisen Expired - Fee Related DE69533567T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28796594A 1994-08-09 1994-08-09
US287965 1994-08-09

Publications (2)

Publication Number Publication Date
DE69533567D1 true DE69533567D1 (de) 2004-11-04
DE69533567T2 DE69533567T2 (de) 2005-11-24

Family

ID=23105146

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69533567T Expired - Fee Related DE69533567T2 (de) 1994-08-09 1995-07-27 Vorrichtung und Verfahren zum Auffinden von False-Timing-Paths in digitalen Schaltkreisen

Country Status (4)

Country Link
US (1) US5675728A (de)
EP (1) EP0697668B1 (de)
JP (1) JPH08180098A (de)
DE (1) DE69533567T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3246865B2 (ja) * 1996-05-10 2002-01-15 株式会社東芝 スタティックタイミング解析装置及びその方法
US6018813A (en) * 1997-04-21 2000-01-25 Nec Usa, Inc. Identification and test generation for primitive faults
US6131080A (en) * 1998-08-17 2000-10-10 Motorola, Inc. Method of monitoring a computer simulation of an electrical circuit
JP2000133718A (ja) * 1998-10-23 2000-05-12 Mitsubishi Electric Corp 配線容量改善支援装置、配線容量改善支援方法および配線容量改善支援プログラムを記録した媒体
US6625745B1 (en) * 1999-03-17 2003-09-23 Hewlett-Packard Development Co.Lp Network component failure identification with minimal testing
JP3370304B2 (ja) 2000-01-28 2003-01-27 シャープ株式会社 高位合成システム、高位合成方法、および、高位合成方法の実施に使用される記録媒体
US6952812B2 (en) * 2001-02-13 2005-10-04 Freescale Semiconductor, Inc. Design analysis tool for path extraction and false path identification and method thereof
JP4128131B2 (ja) * 2003-11-19 2008-07-30 富士通株式会社 フォールスパス検出プログラム
JP2005293349A (ja) * 2004-04-01 2005-10-20 Nec Electronics Corp 回路設計支援システム、設計方法及びプログラム
US7509605B2 (en) * 2005-12-12 2009-03-24 International Business Machines Corporation Extending incremental verification of circuit design to encompass verification restraints
DE602006011177D1 (de) * 2006-10-23 2010-01-28 Onespin Solutions Gmbh Überprüfung und Erzeugung von Zeitfehlern
US8818741B2 (en) * 2009-04-03 2014-08-26 Raytheon Company Method of detecting changes in integrated circuits using thermally imaged test patterns
JP5359655B2 (ja) * 2009-07-30 2013-12-04 富士通セミコンダクター株式会社 生成方法
US10275561B2 (en) 2016-05-27 2019-04-30 Taiwan Semiconductor Manufacturing Company Limited Method for eliminating false paths of a circuit unit to be implemented using a system
US10331826B2 (en) 2017-04-20 2019-06-25 Texas Instruments Incorporated False path timing exception handler circuit

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4556840A (en) * 1981-10-30 1985-12-03 Honeywell Information Systems Inc. Method for testing electronic assemblies
US4763289A (en) * 1985-12-31 1988-08-09 International Business Machines Corporation Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits
ATE87754T1 (de) * 1986-06-06 1993-04-15 Siemens Ag Verfahren zur simulation eines verzoegerungsfehlers in einer logikschaltung und anordnungen zur durchfuehrung des verfahrens.
JPH0682520B2 (ja) * 1987-07-31 1994-10-19 株式会社東芝 半導体メモリ
US4924430A (en) * 1988-01-28 1990-05-08 Teradyne, Inc. Static timing analysis of semiconductor digital circuits
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
US5023485A (en) * 1989-12-04 1991-06-11 Texas Instruments Incorporated Method and circuitry for testing a programmable logic device
US5200907A (en) * 1990-04-16 1993-04-06 Tran Dzung J Transmission gate logic design method
US5191541A (en) * 1990-05-14 1993-03-02 Sun Microsystems, Inc. Method and apparatus to improve static path analysis of digital circuits
US5319646A (en) * 1991-09-18 1994-06-07 Ncr Corporation Boundary-scan output cell with non-critical enable path
US5377197A (en) * 1992-02-24 1994-12-27 University Of Illinois Method for automatically generating test vectors for digital integrated circuits
US5387825A (en) * 1992-08-20 1995-02-07 Texas Instruments Incorporated Glitch-eliminator circuit
US5448497A (en) * 1992-09-08 1995-09-05 Nec Research Institute, Inc. Exploiting multi-cycle false paths in the performance optimization of sequential circuits
EP0600608B1 (de) * 1992-10-29 1999-12-22 Altera Corporation Verfahren zum Prüfen von Entwürfen für programmierbare Logikschaltungen
US5452239A (en) * 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system

Also Published As

Publication number Publication date
DE69533567T2 (de) 2005-11-24
EP0697668B1 (de) 2004-09-29
EP0697668A1 (de) 1996-02-21
US5675728A (en) 1997-10-07
JPH08180098A (ja) 1996-07-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee