DE69905750D1 - Einrichtung und verfahren zum kalibrieren von laufzeitunterschieden - Google Patents

Einrichtung und verfahren zum kalibrieren von laufzeitunterschieden

Info

Publication number
DE69905750D1
DE69905750D1 DE69905750T DE69905750T DE69905750D1 DE 69905750 D1 DE69905750 D1 DE 69905750D1 DE 69905750 T DE69905750 T DE 69905750T DE 69905750 T DE69905750 T DE 69905750T DE 69905750 D1 DE69905750 D1 DE 69905750D1
Authority
DE
Germany
Prior art keywords
time
calibrating
difference
calibrating difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69905750T
Other languages
English (en)
Other versions
DE69905750T2 (de
Inventor
Ilya Valerievich Klotchkov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Benhov GmbH LLC
Original Assignee
Acuid Corp Guernsey Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acuid Corp Guernsey Ltd filed Critical Acuid Corp Guernsey Ltd
Publication of DE69905750D1 publication Critical patent/DE69905750D1/de
Application granted granted Critical
Publication of DE69905750T2 publication Critical patent/DE69905750T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69905750T 1998-06-29 1999-06-10 Einrichtung und verfahren zum kalibrieren von laufzeitunterschieden Expired - Lifetime DE69905750T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
WOPCT/RU98/00204 1998-06-29
PCT/RU1998/000204 WO2000000836A1 (en) 1998-06-29 1998-06-29 A skew calibration means and a method of skew calibration
PCT/RU1999/000194 WO2000000837A1 (en) 1998-06-29 1999-06-10 A skew calibration means and a method of skew calibration

Publications (2)

Publication Number Publication Date
DE69905750D1 true DE69905750D1 (de) 2003-04-10
DE69905750T2 DE69905750T2 (de) 2004-02-19

Family

ID=20130236

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69905750T Expired - Lifetime DE69905750T2 (de) 1998-06-29 1999-06-10 Einrichtung und verfahren zum kalibrieren von laufzeitunterschieden

Country Status (7)

Country Link
US (1) US6298465B1 (de)
EP (1) EP1131645B1 (de)
JP (1) JP2002519675A (de)
AU (2) AU9654198A (de)
CA (1) CA2346883A1 (de)
DE (1) DE69905750T2 (de)
WO (2) WO2000000836A1 (de)

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US6374371B1 (en) * 1998-03-18 2002-04-16 Micron Technology, Inc. Method and apparatus for monitoring component latency drifts
US6414960B1 (en) * 1998-12-29 2002-07-02 International Business Machines Corp. Apparatus and method of in-service audio/video synchronization testing
JP4118463B2 (ja) * 1999-07-23 2008-07-16 株式会社アドバンテスト タイミング保持機能を搭載したｉｃ試験装置
JP3329323B2 (ja) * 1999-12-22 2002-09-30 日本電気株式会社 波形なまり検証方法及び波形なまり検証装置
US6492797B1 (en) * 2000-02-28 2002-12-10 Schlumberger Technologies, Inc. Socket calibration method and apparatus
US6889357B1 (en) * 2000-05-10 2005-05-03 Micron Technology, Inc. Timing calibration pattern for SLDRAM
US6622103B1 (en) * 2000-06-20 2003-09-16 Formfactor, Inc. System for calibrating timing of an integrated circuit wafer tester
WO2002003146A2 (en) 2000-07-06 2002-01-10 Igor Anatolievich Abrosimov Interface device with stored data on transmission lines characteristics
AU2001290402A1 (en) * 2000-10-31 2002-05-21 Igor Anatolievich Abrosimov Channel time calibration means
US6721920B2 (en) * 2001-06-07 2004-04-13 Agilent Technologies, Inc. Systems and methods for facilitating testing of pad drivers of integrated circuits
JP2003100100A (ja) * 2001-07-19 2003-04-04 Mitsubishi Electric Corp 半導体集積回路装置
US6570397B2 (en) 2001-08-07 2003-05-27 Agilent Technologies, Inc. Timing calibration and timing calibration verification of electronic circuit testers
JP4776124B2 (ja) * 2001-09-28 2011-09-21 ルネサスエレクトロニクス株式会社 半導体集積回路装置、配線生成方法及び配線生成装置
US20030097541A1 (en) * 2001-11-19 2003-05-22 Abrosimov Igor Anatolievich Latency tolerant processing equipment
US6734703B1 (en) * 2002-07-19 2004-05-11 Xilinx, Inc. Circuits and methods for analyzing timing characteristics of sequential logic elements
US20050086037A1 (en) * 2003-09-29 2005-04-21 Pauley Robert S. Memory device load simulator
KR100733184B1 (ko) * 2004-01-09 2007-06-28 주식회사 아도반테스토 타이밍 클록 교정 방법
JP4025731B2 (ja) * 2004-01-26 2007-12-26 エルピーダメモリ株式会社 タイミング補正装置、タイミング補正方法及びデバイス評価装置
US20060059382A1 (en) * 2004-09-10 2006-03-16 Schneider Glenn H Method of skew adjustment
DE102004057772B3 (de) * 2004-11-30 2006-05-24 Infineon Technologies Ag Einsetzbare Kalibriervorrichtung
DE102005051814A1 (de) * 2005-10-28 2007-05-03 Infineon Technologies Ag Elektronische Testvorrichtung mit erhöhter Taktfrequenz und Verfahren zum Erhöhen der Taktfrequenz im Testsystem
DE112007001595T5 (de) * 2006-06-30 2009-07-30 Teradyne, Inc., North Reading Kalibrierungsvorrichtung
DE102006051135B4 (de) * 2006-10-30 2016-11-17 Polaris Innovations Ltd. Test-Verfahren, sowie Halbleiter-Bauelement, insbesondere Daten-Zwischenspeicher-Bauelement
DE102007010284A1 (de) 2007-03-02 2008-09-04 Qimonda Ag Schnittstellenvorrichtung, Schaltungsmodul, Schaltungssystem, Vorrichtung für eine Datenkommunikation und Verfahren zum Kalibrieren eines Schaltungsmoduls
US9166750B1 (en) * 2013-03-08 2015-10-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Soft decision analyzer and method
US9632136B2 (en) * 2013-04-04 2017-04-25 International Business Machines Corporation Precise estimation of arrival time of switching events close in time and space
US9324455B2 (en) * 2014-05-27 2016-04-26 Freescale Semiconductor, Inc. Apparatus for measuring signal skew of asynchronous flash memory controller
US10069503B2 (en) * 2016-05-30 2018-09-04 Microsemi Semiconductor Ulc Method of speeding up output alignment in a digital phase locked loop
US10564219B2 (en) * 2017-07-27 2020-02-18 Teradyne, Inc. Time-aligning communication channels
DE112020000035T5 (de) * 2019-01-22 2020-12-31 Advantest Corporation Automatisierte prüfeinrichtung zum prüfen eines oder mehrerer prüfobjekte, verfahren zum automatisierten prüfen eines oder mehrerer prüfobjekte und computerprogramm zur handhabung von befehlsfehlern
US11360143B2 (en) 2020-10-29 2022-06-14 Stmicroelectronics International N.V. High speed debug-delay compensation in external tool
CN116613084B (zh) * 2023-07-17 2024-02-23 深圳市思远半导体有限公司 芯片、测试机台、芯片内部比较器的校准方法及相关设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900006283B1 (ko) * 1981-10-26 1990-08-27 넬슨 스톤 전자 검사 장치내의 핀 전자 인터페이스 회로의 자동 디-스큐우잉(De-skewing)방법 및 장치
US4806852A (en) * 1984-09-07 1989-02-21 Megatest Corporation Automatic test system with enhanced performance of timing generators
US4903024A (en) * 1987-10-23 1990-02-20 Westinghouse Electric Corp. A/D converter system with error correction and calibration apparatus and method
JP2688941B2 (ja) * 1988-08-29 1997-12-10 株式会社アドバンテスト 位相補正装置
US5748642A (en) * 1995-09-25 1998-05-05 Credence Systems Corporation Parallel processing integrated circuit tester
US5982827A (en) * 1997-05-14 1999-11-09 Hewlett-Packard Co. Means for virtual deskewing of high/intermediate/low DUT data
US6073259A (en) * 1997-08-05 2000-06-06 Teradyne, Inc. Low cost CMOS tester with high channel density
US5854797A (en) * 1997-08-05 1998-12-29 Teradyne, Inc. Tester with fast refire recovery time

Also Published As

Publication number Publication date
CA2346883A1 (en) 2000-01-06
US6298465B1 (en) 2001-10-02
AU9654198A (en) 2000-01-17
WO2000000836A1 (en) 2000-01-06
AU4937999A (en) 2000-01-17
EP1131645A1 (de) 2001-09-12
EP1131645B1 (de) 2003-03-05
JP2002519675A (ja) 2002-07-02
WO2000000837A1 (en) 2000-01-06
DE69905750T2 (de) 2004-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PATENTICA IP LTD., MANCHESTER, GB

8327 Change in the person/name/address of the patent owner

Owner name: TOP BOX ASSETS L.L.C., WILMINGTON, DEL., US

8328 Change in the person/name/address of the agent

Representative=s name: DENDORFER & HERRMANN PATENTANWAELTE PARTNERSCHAFT,