DE68917325D1 - Verfahren und Vorrichtung zum Schreiben gegenseitiger verriegelter Variablen in einen integrierten Cachespeicher. - Google Patents

Verfahren und Vorrichtung zum Schreiben gegenseitiger verriegelter Variablen in einen integrierten Cachespeicher.

Info

Publication number
DE68917325D1
DE68917325D1 DE68917325T DE68917325T DE68917325D1 DE 68917325 D1 DE68917325 D1 DE 68917325D1 DE 68917325 T DE68917325 T DE 68917325T DE 68917325 T DE68917325 T DE 68917325T DE 68917325 D1 DE68917325 D1 DE 68917325D1
Authority
DE
Germany
Prior art keywords
variables
interlock
methods
interlocked
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68917325T
Other languages
English (en)
Other versions
DE68917325T2 (de
Inventor
Gigy Baror
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE68917325D1 publication Critical patent/DE68917325D1/de
Application granted granted Critical
Publication of DE68917325T2 publication Critical patent/DE68917325T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip
DE68917325T 1988-01-20 1989-01-18 Verfahren und Vorrichtung zum Schreiben gegenseitiger verriegelter Variablen in einen integrierten Cachespeicher. Expired - Lifetime DE68917325T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/146,020 US5136691A (en) 1988-01-20 1988-01-20 Methods and apparatus for caching interlock variables in an integrated cache memory

Publications (2)

Publication Number Publication Date
DE68917325D1 true DE68917325D1 (de) 1994-09-15
DE68917325T2 DE68917325T2 (de) 1995-03-02

Family

ID=22515558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68917325T Expired - Lifetime DE68917325T2 (de) 1988-01-20 1989-01-18 Verfahren und Vorrichtung zum Schreiben gegenseitiger verriegelter Variablen in einen integrierten Cachespeicher.

Country Status (6)

Country Link
US (1) US5136691A (de)
EP (1) EP0325419B1 (de)
JP (1) JP3158161B2 (de)
AT (1) ATE109909T1 (de)
DE (1) DE68917325T2 (de)
ES (1) ES2057099T3 (de)

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US5838946A (en) * 1990-04-14 1998-11-17 Sun Microsystems, Inc. Method and apparatus for accomplishing processor read of selected information through a cache memory
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US5835934A (en) * 1993-10-12 1998-11-10 Texas Instruments Incorporated Method and apparatus of low power cache operation with a tag hit enablement
US5577226A (en) * 1994-05-06 1996-11-19 Eec Systems, Inc. Method and system for coherently caching I/O devices across a network
US5490270A (en) * 1994-06-16 1996-02-06 International Business Machines Corporation Simultaneous updates to the modification time attribute of a shared file in a cluster having a server and client nodes
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US5895496A (en) * 1994-11-18 1999-04-20 Apple Computer, Inc. System for an method of efficiently controlling memory accesses in a multiprocessor computer system
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US6061731A (en) * 1994-12-06 2000-05-09 Thunderwave, Inc. Read only linear stream based cache system
US5761722A (en) * 1995-01-30 1998-06-02 Sun Microsystems, Inc. Method and apparatus for solving the stale data problem occurring in data access performed with data caches
US5890216A (en) * 1995-04-21 1999-03-30 International Business Machines Corporation Apparatus and method for decreasing the access time to non-cacheable address space in a computer system
US6131152A (en) * 1996-05-15 2000-10-10 Philips Electronics North America Corporation Planar cache layout and instruction stream therefor
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US6061762A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Apparatus and method for separately layering cache and architectural specific functions in different operational controllers
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US5974507A (en) * 1997-04-14 1999-10-26 International Business Machines Corporation Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm
US5978888A (en) * 1997-04-14 1999-11-02 International Business Machines Corporation Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
US6058456A (en) * 1997-04-14 2000-05-02 International Business Machines Corporation Software-managed programmable unified/split caching mechanism for instructions and data
US6098156A (en) * 1997-07-22 2000-08-01 International Business Machines Corporation Method and system for rapid line ownership transfer for multiprocessor updates
US6334173B1 (en) 1997-11-17 2001-12-25 Hyundai Electronics Industries Co. Ltd. Combined cache with main memory and a control method thereof
US6240490B1 (en) 1998-07-20 2001-05-29 International Business Machines Corporation Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment
US6651088B1 (en) * 1999-07-20 2003-11-18 Hewlett-Packard Development Company, L.P. Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
US6460124B1 (en) * 2000-10-20 2002-10-01 Wisconsin Alumni Research Foundation Method of using delays to speed processing of inferred critical program portions
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US7120762B2 (en) * 2001-10-19 2006-10-10 Wisconsin Alumni Research Foundation Concurrent execution of critical sections by eliding ownership of locks
US6839812B2 (en) * 2001-12-21 2005-01-04 Intel Corporation Method and system to cache metadata
US7340569B2 (en) * 2004-02-10 2008-03-04 Wisconsin Alumni Research Foundation Computer architecture providing transactional, lock-free execution of lock-based programs
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US8230180B2 (en) * 2008-06-11 2012-07-24 Samsung Electronics Co., Ltd. Shared memory burst communications
US8839025B2 (en) * 2011-09-30 2014-09-16 Oracle International Corporation Systems and methods for retiring and unretiring cache lines
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CN106293637B (zh) * 2015-05-28 2018-10-30 华为技术有限公司 数据移动、将数据设置为无效的方法、处理器及系统
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EP0325422B1 (de) * 1988-01-20 1996-05-15 Advanced Micro Devices, Inc. Integrierte Cachespeichereinheit
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
ATE109910T1 (de) * 1988-01-20 1994-08-15 Advanced Micro Devices Inc Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen.

Also Published As

Publication number Publication date
JPH01239637A (ja) 1989-09-25
US5136691A (en) 1992-08-04
EP0325419A3 (de) 1991-01-02
ATE109909T1 (de) 1994-08-15
ES2057099T3 (es) 1994-10-16
DE68917325T2 (de) 1995-03-02
EP0325419B1 (de) 1994-08-10
EP0325419A2 (de) 1989-07-26
JP3158161B2 (ja) 2001-04-23

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