ATE109909T1 - Verfahren und vorrichtung zum schreiben gegenseitiger verriegelter variablen in einen integrierten cachespeicher. - Google Patents

Verfahren und vorrichtung zum schreiben gegenseitiger verriegelter variablen in einen integrierten cachespeicher.

Info

Publication number
ATE109909T1
ATE109909T1 AT89300432T AT89300432T ATE109909T1 AT E109909 T1 ATE109909 T1 AT E109909T1 AT 89300432 T AT89300432 T AT 89300432T AT 89300432 T AT89300432 T AT 89300432T AT E109909 T1 ATE109909 T1 AT E109909T1
Authority
AT
Austria
Prior art keywords
variables
writing
interlock
methods
cache
Prior art date
Application number
AT89300432T
Other languages
English (en)
Inventor
Gigy Baror
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE109909T1 publication Critical patent/ATE109909T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0837—Cache consistency protocols with software control, e.g. non-cacheable data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
AT89300432T 1988-01-20 1989-01-18 Verfahren und vorrichtung zum schreiben gegenseitiger verriegelter variablen in einen integrierten cachespeicher. ATE109909T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/146,020 US5136691A (en) 1988-01-20 1988-01-20 Methods and apparatus for caching interlock variables in an integrated cache memory

Publications (1)

Publication Number Publication Date
ATE109909T1 true ATE109909T1 (de) 1994-08-15

Family

ID=22515558

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89300432T ATE109909T1 (de) 1988-01-20 1989-01-18 Verfahren und vorrichtung zum schreiben gegenseitiger verriegelter variablen in einen integrierten cachespeicher.

Country Status (6)

Country Link
US (1) US5136691A (de)
EP (1) EP0325419B1 (de)
JP (1) JP3158161B2 (de)
AT (1) ATE109909T1 (de)
DE (1) DE68917325T2 (de)
ES (1) ES2057099T3 (de)

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CN106293637B (zh) * 2015-05-28 2018-10-30 华为技术有限公司 数据移动、将数据设置为无效的方法、处理器及系统
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ATE109910T1 (de) * 1988-01-20 1994-08-15 Advanced Micro Devices Inc Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen.

Also Published As

Publication number Publication date
EP0325419B1 (de) 1994-08-10
DE68917325D1 (de) 1994-09-15
DE68917325T2 (de) 1995-03-02
EP0325419A2 (de) 1989-07-26
US5136691A (en) 1992-08-04
JP3158161B2 (ja) 2001-04-23
ES2057099T3 (es) 1994-10-16
EP0325419A3 (de) 1991-01-02
JPH01239637A (ja) 1989-09-25

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Legal Events

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UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee