DE60334046D1 - Verfahren zur Bereitstellung einer elektrischen Verbindung unter Verwendung eines abmontierbare Substrates - Google Patents

Verfahren zur Bereitstellung einer elektrischen Verbindung unter Verwendung eines abmontierbare Substrates

Info

Publication number
DE60334046D1
DE60334046D1 DE60334046T DE60334046T DE60334046D1 DE 60334046 D1 DE60334046 D1 DE 60334046D1 DE 60334046 T DE60334046 T DE 60334046T DE 60334046 T DE60334046 T DE 60334046T DE 60334046 D1 DE60334046 D1 DE 60334046D1
Authority
DE
Germany
Prior art keywords
providing
electrical connection
demountable
substrate
demountable substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60334046T
Other languages
German (de)
English (en)
Inventor
Brian E Lemoff
Lisa A Buckman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Avago Technologies General IP Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avago Technologies General IP Singapore Pte Ltd filed Critical Avago Technologies General IP Singapore Pte Ltd
Application granted granted Critical
Publication of DE60334046D1 publication Critical patent/DE60334046D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/148—Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
DE60334046T 2002-05-17 2003-02-03 Verfahren zur Bereitstellung einer elektrischen Verbindung unter Verwendung eines abmontierbare Substrates Expired - Lifetime DE60334046D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/150,303 US6882044B2 (en) 2002-05-17 2002-05-17 High speed electronic interconnection using a detachable substrate

Publications (1)

Publication Number Publication Date
DE60334046D1 true DE60334046D1 (de) 2010-10-21

Family

ID=29269793

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60334046T Expired - Lifetime DE60334046D1 (de) 2002-05-17 2003-02-03 Verfahren zur Bereitstellung einer elektrischen Verbindung unter Verwendung eines abmontierbare Substrates

Country Status (4)

Country Link
US (1) US6882044B2 (https=)
EP (1) EP1363327B1 (https=)
JP (1) JP2004006871A (https=)
DE (1) DE60334046D1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079572A1 (en) 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US7304362B2 (en) * 2002-05-20 2007-12-04 Stmicroelectronics, Inc. Molded integrated circuit package with exposed active area
JP4866625B2 (ja) * 2006-02-15 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置
WO2008059571A1 (en) * 2006-11-15 2008-05-22 Panasonic Corporation Circuit board connection structure and circuit board
CN101986770B (zh) * 2010-08-06 2013-04-03 深圳崇达多层线路板有限公司 多阶高密度线路板对位孔及制作方法
DE102014217985A1 (de) * 2014-09-09 2016-03-10 Robert Bosch Gmbh Verfahren zum Herstellen eines Bondpads, Bondpad und Bondverfahren

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483570A (https=) * 1965-06-23 1967-09-06
GB1223704A (en) * 1967-04-19 1971-03-03 Hitachi Ltd Semiconductor device
JPS575356A (en) * 1980-06-13 1982-01-12 Toshiba Corp Hybrid integrated circuit device
US5184207A (en) 1988-12-07 1993-02-02 Tribotech Semiconductor die packages having lead support frame
JP2626203B2 (ja) * 1990-08-03 1997-07-02 富士ゼロックス株式会社 電子写真感光体の製造方法
US5060052A (en) * 1990-09-04 1991-10-22 Motorola, Inc. TAB bonded semiconductor device having off-chip power and ground distribution
US5309322A (en) 1992-10-13 1994-05-03 Motorola, Inc. Leadframe strip for semiconductor packages and method
DE19603444C2 (de) * 1996-01-31 2003-04-24 Siemens Ag LED-Vorrichtung mit mindestens zwei LEDs
KR19980020726A (ko) 1996-09-11 1998-06-25 김광호 칩 스케일의 볼 그리드 어레이 패키지 및 그의 제조 방법
US6177722B1 (en) * 1998-04-21 2001-01-23 Atmel Corporation Leadless array package
US6146813A (en) * 1999-01-13 2000-11-14 Applied Kinetics Inc. Method and shunting and deshunting an electrical component and a shuntable/shunted electrical component
US6242280B1 (en) * 1999-06-30 2001-06-05 Agilent Technologies, Inc. Method of interconnecting an electronic device
JP4441974B2 (ja) * 2000-03-24 2010-03-31 ソニー株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2004006871A (ja) 2004-01-08
EP1363327A2 (en) 2003-11-19
US20030213963A1 (en) 2003-11-20
EP1363327B1 (en) 2010-09-08
US6882044B2 (en) 2005-04-19
EP1363327A3 (en) 2006-02-01

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