DE60302406D1 - Verfahren zur Herstellung einer Schaltung unter Verwendung von Prägeverfahren - Google Patents

Verfahren zur Herstellung einer Schaltung unter Verwendung von Prägeverfahren

Info

Publication number
DE60302406D1
DE60302406D1 DE60302406T DE60302406T DE60302406D1 DE 60302406 D1 DE60302406 D1 DE 60302406D1 DE 60302406 T DE60302406 T DE 60302406T DE 60302406 T DE60302406 T DE 60302406T DE 60302406 D1 DE60302406 D1 DE 60302406D1
Authority
DE
Germany
Prior art keywords
producing
circuit
embossing methods
embossing
methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60302406T
Other languages
English (en)
Other versions
DE60302406T2 (de
Inventor
Craig Perlov
Carl Taussig
Ping Mei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Application granted granted Critical
Publication of DE60302406D1 publication Critical patent/DE60302406D1/de
Publication of DE60302406T2 publication Critical patent/DE60302406T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Shaping Of Tube Ends By Bending Or Straightening (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Drying Of Semiconductors (AREA)
DE60302406T 2002-09-17 2003-09-09 Verfahren zur Herstellung einer Schaltung unter Verwendung von Prägeverfahren Expired - Fee Related DE60302406T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US244862 2002-09-17
US10/244,862 US6887792B2 (en) 2002-09-17 2002-09-17 Embossed mask lithography

Publications (2)

Publication Number Publication Date
DE60302406D1 true DE60302406D1 (de) 2005-12-29
DE60302406T2 DE60302406T2 (de) 2006-07-27

Family

ID=31946397

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60302406T Expired - Fee Related DE60302406T2 (de) 2002-09-17 2003-09-09 Verfahren zur Herstellung einer Schaltung unter Verwendung von Prägeverfahren

Country Status (7)

Country Link
US (2) US6887792B2 (de)
EP (1) EP1400848B1 (de)
JP (1) JP2004111933A (de)
KR (1) KR20040030298A (de)
CN (1) CN100340922C (de)
DE (1) DE60302406T2 (de)
TW (1) TW200405130A (de)

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US7259106B2 (en) * 2004-09-10 2007-08-21 Versatilis Llc Method of making a microelectronic and/or optoelectronic circuitry sheet
US20060105550A1 (en) * 2004-11-17 2006-05-18 Manish Sharma Method of depositing material on a substrate for a device
US7676088B2 (en) * 2004-12-23 2010-03-09 Asml Netherlands B.V. Imprint lithography
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US7871927B2 (en) * 2006-10-17 2011-01-18 Cufer Asset Ltd. L.L.C. Wafer via formation
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US8466068B2 (en) 2007-12-31 2013-06-18 Sandisk 3D Llc Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US8138412B2 (en) * 2009-05-12 2012-03-20 Hewlett-Packard Development Company, L.P. Flexible electrical substrate
KR200452471Y1 (ko) 2010-01-26 2011-03-03 (주)코리아스타텍 엠보싱 지그
US8437174B2 (en) 2010-02-15 2013-05-07 Micron Technology, Inc. Memcapacitor devices, field effect transistor devices, non-volatile memory arrays, and methods of programming
US8416609B2 (en) * 2010-02-15 2013-04-09 Micron Technology, Inc. Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, methods of writing to and reading from a memory cell, and computer systems
US8634224B2 (en) 2010-08-12 2014-01-21 Micron Technology, Inc. Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and reading from a memory cell, and methods of programming a memory cell
US8409915B2 (en) 2010-09-20 2013-04-02 Micron Technology, Inc. Methods of forming memory cells
US8877531B2 (en) 2010-09-27 2014-11-04 Applied Materials, Inc. Electronic apparatus
DE102010042567B3 (de) * 2010-10-18 2012-03-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines Chip-Package und Chip-Package
WO2012158709A1 (en) 2011-05-16 2012-11-22 The Board Of Trustees Of The University Of Illinois Thermally managed led arrays assembled by printing
WO2013029564A1 (zh) * 2011-09-01 2013-03-07 Zhang Guobiao 三维印录存储器
CN107978516A (zh) * 2016-10-24 2018-05-01 杭州海存信息技术有限公司 基于三维偏置印录存储器的三维封装
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CN102508410A (zh) * 2011-10-27 2012-06-20 南京大学 一种三明治结构复合纳米压印模板及其制备方法
CN103594471B (zh) * 2012-08-17 2016-12-21 成都海存艾匹科技有限公司 三维可写印录存储器
CN103681679A (zh) * 2012-08-30 2014-03-26 成都海存艾匹科技有限公司 三维偏置印录存储器
CN103681511B (zh) * 2012-09-01 2016-02-03 成都海存艾匹科技有限公司 压印存储器
CN104751894A (zh) * 2012-09-02 2015-07-01 杭州海存信息技术有限公司 压印存储器
KR102047922B1 (ko) 2013-02-07 2019-11-25 삼성디스플레이 주식회사 플렉서블 기판, 플렉서블 기판의 제조 방법, 플렉서블 표시 장치, 및 플렉서블 표시 장치 제조 방법
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Also Published As

Publication number Publication date
US20040256352A1 (en) 2004-12-23
DE60302406T2 (de) 2006-07-27
US20040054980A1 (en) 2004-03-18
KR20040030298A (ko) 2004-04-09
EP1400848B1 (de) 2005-11-23
JP2004111933A (ja) 2004-04-08
US7304364B2 (en) 2007-12-04
TW200405130A (en) 2004-04-01
US6887792B2 (en) 2005-05-03
CN1487362A (zh) 2004-04-07
CN100340922C (zh) 2007-10-03
EP1400848A1 (de) 2004-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee