DE60324429D1 - Kanal mit verschiedenen Taktregionen - Google Patents

Kanal mit verschiedenen Taktregionen

Info

Publication number
DE60324429D1
DE60324429D1 DE60324429T DE60324429T DE60324429D1 DE 60324429 D1 DE60324429 D1 DE 60324429D1 DE 60324429 T DE60324429 T DE 60324429T DE 60324429 T DE60324429 T DE 60324429T DE 60324429 D1 DE60324429 D1 DE 60324429D1
Authority
DE
Germany
Prior art keywords
channel
different clock
clock regions
regions
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60324429T
Other languages
English (en)
Inventor
Thomas Henkel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verigy Singapore Pte Ltd
Original Assignee
Verigy Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verigy Singapore Pte Ltd filed Critical Verigy Singapore Pte Ltd
Application granted granted Critical
Publication of DE60324429D1 publication Critical patent/DE60324429D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60324429T 2003-09-17 2003-09-17 Kanal mit verschiedenen Taktregionen Expired - Lifetime DE60324429D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03020983A EP1517152B1 (de) 2003-09-17 2003-09-17 Kanal mit verschiedenen Taktregionen

Publications (1)

Publication Number Publication Date
DE60324429D1 true DE60324429D1 (de) 2008-12-11

Family

ID=34178418

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60324429T Expired - Lifetime DE60324429D1 (de) 2003-09-17 2003-09-17 Kanal mit verschiedenen Taktregionen

Country Status (4)

Country Link
US (1) US7346102B2 (de)
EP (1) EP1517152B1 (de)
JP (1) JP2005091362A (de)
DE (1) DE60324429D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102124357A (zh) * 2008-08-19 2011-07-13 爱德万测试株式会社 测试装置及测试方法
GB2513529A (en) * 2012-11-15 2014-11-05 Ibm System and method of low latency data tranfer between clock domains operated in various synchronization modes

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1251575A (en) * 1985-12-18 1989-03-21 A. Keith Jeffrey Automatic test system having a "true tester-per-pin" architecture
JPH0812230B2 (ja) * 1988-09-06 1996-02-07 株式会社日立製作所 Ｉｃ試験装置
US5448715A (en) * 1992-07-29 1995-09-05 Hewlett-Packard Company Dual clock domain interface between CPU and memory bus
US5311486A (en) * 1992-09-11 1994-05-10 Ltx Corporation Timing generation in an automatic electrical test system
JP3505011B2 (ja) * 1995-06-22 2004-03-08 株式会社アドバンテスト 高精度信号発生回路
DE69613560T2 (de) * 1996-04-30 2002-03-14 Agilent Technologies Inc Ein Prüfgerät für elektronische Schaltkreise oder Platinen mit komprimierten Datenfolgen
JPH1073638A (ja) * 1996-08-29 1998-03-17 Asia Electron Inc 半導体試験装置
JP2910694B2 (ja) * 1996-09-12 1999-06-23 日本電気株式会社 Ｉ／ｏコントローラ
US5835752A (en) * 1996-10-18 1998-11-10 Samsung Electronics Co. Ltd. PCI interface synchronization
JPH10160808A (ja) * 1996-11-28 1998-06-19 Advantest Corp Ｉｃ試験装置
JPH10240560A (ja) * 1997-02-26 1998-09-11 Toshiba Corp 波形信号処理装置
US6055644A (en) * 1997-05-30 2000-04-25 Hewlett-Packard Company Multi-channel architecture with channel independent clock signals
JP3228708B2 (ja) * 1998-04-03 2001-11-12 パイオニア株式会社 伝送システムにおける受信インターフェース装置
US6553529B1 (en) * 1999-07-23 2003-04-22 Teradyne, Inc. Low cost timing system for highly accurate multi-modal semiconductor testing
JP2001133525A (ja) * 1999-11-05 2001-05-18 Hitachi Electronics Eng Co Ltd Ｉｃテスタのタイミングパルス発生回路およびｉｃテスタ
US6801869B2 (en) * 2000-02-22 2004-10-05 Mccord Don Method and system for wafer and device-level testing of an integrated circuit
US6404218B1 (en) * 2000-04-24 2002-06-11 Advantest Corp. Multiple end of test signal for event based test system
JP4672194B2 (ja) * 2001-06-22 2011-04-20 富士通株式会社 受信回路
JP2003057318A (ja) * 2001-08-10 2003-02-26 Advantest Corp 半導体試験装置
JP2003203495A (ja) * 2002-01-07 2003-07-18 Mitsubishi Electric Corp 半導体記憶装置の試験装置及び試験方法
US6590826B1 (en) * 2002-01-22 2003-07-08 Xilinx, Inc. Self-addressing FIFO

Also Published As

Publication number Publication date
EP1517152B1 (de) 2008-10-29
US20050069030A1 (en) 2005-03-31
EP1517152A1 (de) 2005-03-23
US7346102B2 (en) 2008-03-18
JP2005091362A (ja) 2005-04-07

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