DE60321612D1 - Verfahren und Vorrichtung zur Dateninversion in einem Speicher - Google Patents

Verfahren und Vorrichtung zur Dateninversion in einem Speicher

Info

Publication number
DE60321612D1
DE60321612D1 DE60321612T DE60321612T DE60321612D1 DE 60321612 D1 DE60321612 D1 DE 60321612D1 DE 60321612 T DE60321612 T DE 60321612T DE 60321612 T DE60321612 T DE 60321612T DE 60321612 D1 DE60321612 D1 DE 60321612D1
Authority
DE
Germany
Prior art keywords
memory
data inversion
inversion
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60321612T
Other languages
English (en)
Inventor
Joseph Macri
Oleg Drapkin
Grigori Temkine
Osamu Nagashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Micron Memory Japan Ltd
Original Assignee
ATI Technologies ULC
Elpida Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI Technologies ULC, Elpida Memory Inc filed Critical ATI Technologies ULC
Application granted granted Critical
Publication of DE60321612D1 publication Critical patent/DE60321612D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE60321612T 2002-02-08 2003-02-10 Verfahren und Vorrichtung zur Dateninversion in einem Speicher Expired - Lifetime DE60321612D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35528902P 2002-02-08 2002-02-08

Publications (1)

Publication Number Publication Date
DE60321612D1 true DE60321612D1 (de) 2008-07-31

Family

ID=27663295

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60321612T Expired - Lifetime DE60321612D1 (de) 2002-02-08 2003-02-10 Verfahren und Vorrichtung zur Dateninversion in einem Speicher

Country Status (3)

Country Link
US (4) US6671212B2 (de)
EP (1) EP1336972B1 (de)
DE (1) DE60321612D1 (de)

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US7869525B2 (en) * 2005-08-01 2011-01-11 Ati Technologies, Inc. Dynamic bus inversion method and system
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US20090091968A1 (en) * 2007-10-08 2009-04-09 Stefan Dietrich Integrated circuit including a memory having a data inversion circuit
US8078795B2 (en) 2008-01-31 2011-12-13 Dell Products L.P. Methods and media for writing data to flash memory
US8219740B2 (en) * 2008-06-25 2012-07-10 International Business Machines Corporation Flash sector seeding to reduce program times
US9646177B2 (en) * 2011-04-29 2017-05-09 Altera Corporation Systems and methods for preventing data remanence in memory systems
US9275692B2 (en) 2012-02-28 2016-03-01 Micron Technology, Inc. Memory, memory controllers, and methods for dynamically switching a data masking/data bus inversion input
US9928191B2 (en) 2015-07-30 2018-03-27 Advanced Micro Devices, Inc. Communication device with selective encoding
KR102608844B1 (ko) * 2016-06-28 2023-12-05 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법
WO2019000456A1 (zh) * 2017-06-30 2019-01-03 华为技术有限公司 传输数据掩码的方法、内存控制器、内存芯片和计算机系统
CN111986723B (zh) * 2019-05-21 2022-09-02 中芯国际集成电路制造(上海)有限公司 一种只读存储器的数据读写方法和数据读取装置

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Also Published As

Publication number Publication date
US7567467B2 (en) 2009-07-28
EP1336972A1 (de) 2003-08-20
US20030151953A1 (en) 2003-08-14
EP1336972B1 (de) 2008-06-18
US8031538B2 (en) 2011-10-04
US6826095B2 (en) 2004-11-30
US20040090836A1 (en) 2004-05-13
US20090323437A1 (en) 2009-12-31
US6671212B2 (en) 2003-12-30
US20050055491A1 (en) 2005-03-10

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Legal Events

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