DE602004027207D1 - Verfahren und Vorrichtung zur Ablaufsteuerung in einem Mehrprozessor-System - Google Patents

Verfahren und Vorrichtung zur Ablaufsteuerung in einem Mehrprozessor-System

Info

Publication number
DE602004027207D1
DE602004027207D1 DE602004027207T DE602004027207T DE602004027207D1 DE 602004027207 D1 DE602004027207 D1 DE 602004027207D1 DE 602004027207 T DE602004027207 T DE 602004027207T DE 602004027207 T DE602004027207 T DE 602004027207T DE 602004027207 D1 DE602004027207 D1 DE 602004027207D1
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DE
Germany
Prior art keywords
sequence control
multiprocessor system
multiprocessor
sequence
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004027207T
Other languages
English (en)
Inventor
Charles E Pilkington
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE602004027207D1 publication Critical patent/DE602004027207D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
DE602004027207T 2003-12-19 2004-12-14 Verfahren und Vorrichtung zur Ablaufsteuerung in einem Mehrprozessor-System Active DE602004027207D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US53153803P 2003-12-19 2003-12-19
US53150203P 2003-12-19 2003-12-19
US10/967,013 US7802255B2 (en) 2003-12-19 2004-10-15 Thread execution scheduler for multi-processing system and method

Publications (1)

Publication Number Publication Date
DE602004027207D1 true DE602004027207D1 (de) 2010-07-01

Family

ID=34527976

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004027207T Active DE602004027207D1 (de) 2003-12-19 2004-12-14 Verfahren und Vorrichtung zur Ablaufsteuerung in einem Mehrprozessor-System

Country Status (3)

Country Link
US (1) US7802255B2 (de)
EP (1) EP1544737B1 (de)
DE (1) DE602004027207D1 (de)

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Also Published As

Publication number Publication date
US7802255B2 (en) 2010-09-21
EP1544737A1 (de) 2005-06-22
EP1544737B1 (de) 2010-05-19
US20050149936A1 (en) 2005-07-07

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