DE60301295T2 - Verfahren zur Herstellung einer sub-lithographischen Durchgangsleitung - Google Patents

Verfahren zur Herstellung einer sub-lithographischen Durchgangsleitung Download PDF

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Publication number
DE60301295T2
DE60301295T2 DE60301295T DE60301295T DE60301295T2 DE 60301295 T2 DE60301295 T2 DE 60301295T2 DE 60301295 T DE60301295 T DE 60301295T DE 60301295 T DE60301295 T DE 60301295T DE 60301295 T2 DE60301295 T2 DE 60301295T2
Authority
DE
Germany
Prior art keywords
polymer layer
etching
layer
lithographic
polymer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60301295T
Other languages
German (de)
English (en)
Other versions
DE60301295D1 (de
Inventor
Heon Pohang-Si Lee
Thomas C. Anthony
Lung T. Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Application granted granted Critical
Publication of DE60301295D1 publication Critical patent/DE60301295D1/de
Publication of DE60301295T2 publication Critical patent/DE60301295T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE60301295T 2002-04-25 2003-04-22 Verfahren zur Herstellung einer sub-lithographischen Durchgangsleitung Expired - Lifetime DE60301295T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US133605 1998-08-13
US10/133,605 US6673714B2 (en) 2002-04-25 2002-04-25 Method of fabricating a sub-lithographic sized via

Publications (2)

Publication Number Publication Date
DE60301295D1 DE60301295D1 (de) 2005-09-22
DE60301295T2 true DE60301295T2 (de) 2006-08-10

Family

ID=29215620

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60301295T Expired - Lifetime DE60301295T2 (de) 2002-04-25 2003-04-22 Verfahren zur Herstellung einer sub-lithographischen Durchgangsleitung

Country Status (5)

Country Link
US (1) US6673714B2 (https=)
EP (1) EP1359609B1 (https=)
JP (1) JP2003338458A (https=)
CN (1) CN1453640A (https=)
DE (1) DE60301295T2 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6916511B2 (en) * 2002-10-24 2005-07-12 Hewlett-Packard Development Company, L.P. Method of hardening a nano-imprinting stamp
US7384727B2 (en) * 2003-06-26 2008-06-10 Micron Technology, Inc. Semiconductor processing patterning methods
US7026243B2 (en) * 2003-10-20 2006-04-11 Micron Technology, Inc. Methods of forming conductive material silicides by reaction of metal with silicon
US6969677B2 (en) * 2003-10-20 2005-11-29 Micron Technology, Inc. Methods of forming conductive metal silicides by reaction of metal with silicon
US7060625B2 (en) * 2004-01-27 2006-06-13 Hewlett-Packard Development Company, L.P. Imprint stamp
US7462292B2 (en) * 2004-01-27 2008-12-09 Hewlett-Packard Development Company, L.P. Silicon carbide imprint stamp
US7153769B2 (en) * 2004-04-08 2006-12-26 Micron Technology, Inc. Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon
US7241705B2 (en) * 2004-09-01 2007-07-10 Micron Technology, Inc. Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
DE102005008478B3 (de) 2005-02-24 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von sublithographischen Strukturen
KR100869359B1 (ko) * 2006-09-28 2008-11-19 주식회사 하이닉스반도체 반도체 소자의 리세스 게이트 제조 방법
JP5349404B2 (ja) * 2010-05-28 2013-11-20 株式会社東芝 パターン形成方法
WO2012076207A1 (en) * 2010-12-08 2012-06-14 Asml Holding N.V. Electrostatic clamp, lithographic apparatus and method of manufacturing an electrostatic clamp
US11175582B2 (en) * 2015-12-30 2021-11-16 Fujifilm Electronic Materials U.S.A., Inc. Photosensitive stacked structure
CN109065445B (zh) * 2018-07-13 2020-10-09 上海华力集成电路制造有限公司 金属栅极结构的制造方法

Family Cites Families (12)

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JPS58130575A (ja) * 1982-01-29 1983-08-04 Hitachi Ltd 電界効果トランジスタの製造方法
JPS6229175A (ja) * 1985-07-29 1987-02-07 Nippon Telegr & Teleph Corp <Ntt> 電界効果型トランジスタの製造方法
US4670090A (en) * 1986-01-23 1987-06-02 Rockwell International Corporation Method for producing a field effect transistor
EP0252179B1 (en) * 1986-07-11 1992-05-27 International Business Machines Corporation Process for producing undercut mask profiles
US4711701A (en) * 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
US4808545A (en) * 1987-04-20 1989-02-28 International Business Machines Corporation High speed GaAs MESFET having refractory contacts and a self-aligned cold gate fabrication process
DE3879186D1 (de) * 1988-04-19 1993-04-15 Ibm Verfahren zur herstellung von integrierten halbleiterstrukturen welche feldeffekttransistoren mit kanallaengen im submikrometerbereich enthalten.
KR910005400B1 (ko) * 1988-09-05 1991-07-29 재단법인 한국전자통신연구소 다층레지스트를 이용한 자기정합형 갈륨비소 전계효과트랜지스터의 제조방법
JPH06267843A (ja) * 1993-03-10 1994-09-22 Hitachi Ltd パターン形成方法
KR0146246B1 (ko) * 1994-09-26 1998-11-02 김주용 반도체 소자 콘택 제조방법
US5976920A (en) * 1996-07-22 1999-11-02 The United States Of America As Represented By The Secretary Of The Air Force Single layer integrated metal process for high electron mobility transistor (HEMT) and pseudomorphic high electron mobility transistor (PHEMT)
US6036875A (en) * 1997-02-20 2000-03-14 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor device with ultra-fine line geometry

Also Published As

Publication number Publication date
JP2003338458A (ja) 2003-11-28
EP1359609B1 (en) 2005-08-17
CN1453640A (zh) 2003-11-05
EP1359609A3 (en) 2004-03-31
US20030211729A1 (en) 2003-11-13
DE60301295D1 (de) 2005-09-22
EP1359609A2 (en) 2003-11-05
US6673714B2 (en) 2004-01-06

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8364 No opposition during term of opposition