DE60224872D1 - Verschachtelter Taktsignalgenerator mit einer in Reihe geschaltete Verzögerungslemente und Ringzähler aufweisenden Architektur - Google Patents

Verschachtelter Taktsignalgenerator mit einer in Reihe geschaltete Verzögerungslemente und Ringzähler aufweisenden Architektur

Info

Publication number
DE60224872D1
DE60224872D1 DE60224872T DE60224872T DE60224872D1 DE 60224872 D1 DE60224872 D1 DE 60224872D1 DE 60224872 T DE60224872 T DE 60224872T DE 60224872 T DE60224872 T DE 60224872T DE 60224872 D1 DE60224872 D1 DE 60224872D1
Authority
DE
Germany
Prior art keywords
clock signal
signal generator
delay element
series connected
ring counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60224872T
Other languages
English (en)
Other versions
DE60224872T2 (de
Inventor
Robert M Neff
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Application granted granted Critical
Publication of DE60224872D1 publication Critical patent/DE60224872D1/de
Publication of DE60224872T2 publication Critical patent/DE60224872T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE60224872T 2002-02-01 2002-10-16 Verschachtelter Taktsignalgenerator mit einer in Reihe geschaltete Verzögerungslemente und Ringzähler aufweisenden Architektur Expired - Lifetime DE60224872T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/061,504 US6956423B2 (en) 2002-02-01 2002-02-01 Interleaved clock signal generator having serial delay and ring counter architecture
US61504 2002-02-01

Publications (2)

Publication Number Publication Date
DE60224872D1 true DE60224872D1 (de) 2008-03-20
DE60224872T2 DE60224872T2 (de) 2009-01-22

Family

ID=22036205

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60224872T Expired - Lifetime DE60224872T2 (de) 2002-02-01 2002-10-16 Verschachtelter Taktsignalgenerator mit einer in Reihe geschaltete Verzögerungslemente und Ringzähler aufweisenden Architektur

Country Status (3)

Country Link
US (1) US6956423B2 (de)
EP (1) EP1333578B1 (de)
DE (1) DE60224872T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60219152D1 (de) * 2002-07-19 2007-05-10 St Microelectronics Srl Eine mehrphasige synchrone Pipelinestruktur
US7369111B2 (en) 2003-04-29 2008-05-06 Samsung Electronics Co., Ltd. Gate driving circuit and display apparatus having the same
US7653168B2 (en) * 2005-01-12 2010-01-26 Nokia Corporation Digital clock dividing circuit
DE102005015429B3 (de) * 2005-04-04 2006-10-19 Infineon Technologies Ag Takterzeugung für einen zeitversetzt arbeitenden Analog-Digital-Wandler
US7148828B2 (en) * 2005-05-03 2006-12-12 Agilent Technologies, Inc. System and method for timing calibration of time-interleaved data converters
US7642865B2 (en) 2005-12-30 2010-01-05 Stmicroelectronics Pvt. Ltd. System and method for multiple-phase clock generation
CN101841324A (zh) * 2010-06-02 2010-09-22 四川和芯微电子股份有限公司 具有自动复位功能的移位分频器
US10078613B1 (en) * 2014-03-05 2018-09-18 Mellanox Technologies, Ltd. Computing in parallel processing environments
GB2528481B (en) * 2014-07-23 2016-08-17 Ibm Updating of shadow registers in N:1 clock domain
CN104702281B (zh) 2015-03-11 2017-12-05 华为技术有限公司 一种采样时钟产生电路及模数转换器
KR102456587B1 (ko) * 2015-11-09 2022-10-20 에스케이하이닉스 주식회사 래치 회로, 그 래치 기반의 이중 데이터 레이트 링 카운터, 하이브리드 카운팅 장치, 아날로그-디지털 변환 장치, 및 씨모스 이미지 센서
RU2761135C1 (ru) * 2020-12-29 2021-12-06 федеральное государственное автономное образовательное учреждение высшего образования "Национальный исследовательский ядерный университет МИФИ" (НИЯУ МИФИ) Счетчик с сохранением количества единиц
US11990911B2 (en) 2022-03-15 2024-05-21 Qualcomm Incorporated Clock driver for time-interleaved digital-to-analog converter

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1129036A (en) * 1978-05-30 1982-08-03 Colin R. Betts Digital data transmission
US5039950A (en) 1989-07-20 1991-08-13 Eastman Kodak Company Multiple clock synthesizer
JPH04192624A (ja) * 1990-11-22 1992-07-10 Matsushita Electric Ind Co Ltd アナログ信号処理装置を駆動する駆動回路に用いる計数回路
JPH07142997A (ja) 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> ディレイ・ライン較正回路
US5155388A (en) 1990-12-20 1992-10-13 Hewlett-Packard Company Logic gates with controllable time delay
US5268656A (en) * 1992-11-05 1993-12-07 At&T Bell Laboratories Programmable clock skew adjustment circuit
US5477181A (en) 1994-10-13 1995-12-19 National Semiconductor Corporation Programmable multiphase clock divider
US5828717A (en) * 1995-03-28 1998-10-27 Matsushita Electric Industrial Co. Ltd. Time counting circuit and counter circuit
US5847588A (en) 1996-12-30 1998-12-08 Eastman Kodak Company Programmable multiple CCD clock synthesizer
US6259281B1 (en) 1999-05-06 2001-07-10 Agilent Technologies, Inc. Parallel analog sampling circuit and analog-to-digital converter system incorporating clock signal generator generating sub-sampling clock signals with fast and precisely-timed edges
US6275072B1 (en) * 1999-10-07 2001-08-14 Velio Communications, Inc. Combined phase comparator and charge pump circuit

Also Published As

Publication number Publication date
US6956423B2 (en) 2005-10-18
EP1333578A2 (de) 2003-08-06
DE60224872T2 (de) 2009-01-22
EP1333578A3 (de) 2004-03-10
US20030151441A1 (en) 2003-08-14
EP1333578B1 (de) 2008-01-30

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