DE60219152D1 - Eine mehrphasige synchrone Pipelinestruktur - Google Patents

Eine mehrphasige synchrone Pipelinestruktur

Info

Publication number
DE60219152D1
DE60219152D1 DE60219152T DE60219152T DE60219152D1 DE 60219152 D1 DE60219152 D1 DE 60219152D1 DE 60219152 T DE60219152 T DE 60219152T DE 60219152 T DE60219152 T DE 60219152T DE 60219152 D1 DE60219152 D1 DE 60219152D1
Authority
DE
Germany
Prior art keywords
pipeline structure
synchronous pipeline
multiphase synchronous
multiphase
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60219152T
Other languages
English (en)
Inventor
Francesco Pappalardo
Agatino Pennisi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60219152D1 publication Critical patent/DE60219152D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
DE60219152T 2002-07-19 2002-07-19 Eine mehrphasige synchrone Pipelinestruktur Expired - Lifetime DE60219152D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02425469A EP1383042B1 (de) 2002-07-19 2002-07-19 Eine mehrphasige synchrone Pipelinestruktur

Publications (1)

Publication Number Publication Date
DE60219152D1 true DE60219152D1 (de) 2007-05-10

Family

ID=29762765

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60219152T Expired - Lifetime DE60219152D1 (de) 2002-07-19 2002-07-19 Eine mehrphasige synchrone Pipelinestruktur

Country Status (3)

Country Link
US (1) US7143302B2 (de)
EP (1) EP1383042B1 (de)
DE (1) DE60219152D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061485B2 (en) * 2002-10-31 2006-06-13 Hewlett-Packard Development Company, Lp. Method and system for producing a model from optical images
WO2006039711A1 (en) 2004-10-01 2006-04-13 Lockheed Martin Corporation Service layer architecture for memory access system and method
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US8151075B2 (en) * 2010-01-22 2012-04-03 Freescale Semiconductor, Inc. Multiple access type memory and method of operation
US9682112B2 (en) 2013-08-05 2017-06-20 Akay Flavours & Aromatics PVT. LTD Ultrasound-assisted continuous extraction for complete fragmentation of cocoa beans into fractions
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3279337B2 (ja) * 1991-04-12 2002-04-30 ヒューレット・パッカード・カンパニー ねずみ取り論理回路用万能パイプラインラッチ
US5508272A (en) * 1993-06-15 1996-04-16 Bristol-Myers Squibb Company Compounds containing a fused bicycle ring and processes therefor
US5670899A (en) * 1994-11-21 1997-09-23 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
WO1997001811A2 (en) * 1995-06-27 1997-01-16 Philips Electronics N.V. Pipelined data processing circuit
US5873000A (en) * 1996-07-19 1999-02-16 Compaq Computer Corporation System incorporating hot docking and undocking capabilities without requiring a standby or suspend mode by placing local arbiters of system and base into idle state
US5909638A (en) * 1996-08-06 1999-06-01 Maximum Video Systems, Inc. High speed video distribution and manufacturing system
US6917899B2 (en) * 2001-09-21 2005-07-12 Microsoft Corporation System and methods for providing histogram computation in a high precision rasterization data pipeline
US6956423B2 (en) * 2002-02-01 2005-10-18 Agilent Technologies, Inc. Interleaved clock signal generator having serial delay and ring counter architecture

Also Published As

Publication number Publication date
EP1383042B1 (de) 2007-03-28
US7143302B2 (en) 2006-11-28
EP1383042A1 (de) 2004-01-21
US20040103334A1 (en) 2004-05-27

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Legal Events

Date Code Title Description
8332 No legal effect for de